baytrail: program PUNIT memory-mapped base address

Apparently there was another BAR living at 0x5c in the LPC
bridge that mapped the PUNIT registers. EDS 2.0 released
and this register is now documented.

BUG=chrome-os-partner:23085
BRANCH=None
TEST=Built and booted.

Change-Id: I5892c2a14923b57826060e92b4335cb1952ea057
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171612
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4861
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/soc/intel/baytrail/baytrail/iomap.h

@@ -28,6 +28,7 @@
 #define ILB_BASE_ADDRESS		0xfed08000
 #define SPI_BASE_ADDRESS		0xfed01000
 #define MPHY_BASE_ADDRESS		0xfef00000
+#define PUNIT_BASE_ADDRESS		0xfed05000
 #define RCBA_BASE_ADDRESS		0xfed1c000
 
 /* IO Port base */

src/soc/intel/baytrail/baytrail/lpc.h

@@ -29,6 +29,7 @@
 #define IBASE		0x50
 #define SBASE		0x54
 #define MPBASE		0x58
+#define PUBASE		0x5c
 #define UART_CONT	0x80
 #define RCBA		0xf0
 

src/soc/intel/baytrail/romstage/romstage.c

@@ -74,6 +74,8 @@ static void program_base_addresses(void)
 	pci_write_config32(lpc_dev, SBASE, reg);
 	reg = MPHY_BASE_ADDRESS | 2;
 	pci_write_config32(lpc_dev, MPBASE, reg);
+	reg = PUNIT_BASE_ADDRESS | 2;
+	pci_write_config32(lpc_dev, PUBASE, reg);
 	reg = RCBA_BASE_ADDRESS | 1;
 	pci_write_config32(lpc_dev, RCBA, reg);