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baytrail: program PUNIT memory-mapped base address 

Apparently there was another BAR living at 0x5c in the LPC
bridge that mapped the PUNIT registers. EDS 2.0 released
and this register is now documented.

BUG=chrome-os-partner:23085
BRANCH=None
TEST=Built and booted.

Change-Id: I5892c2a14923b57826060e92b4335cb1952ea057
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171612
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4861
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Aaron Durbin 2013-10-03 12:56:37 -05:00 committed by Aaron Durbin
parent 51ca694a97
commit a64ef62ca4
3 changed files with 4 additions and 0 deletions
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1
src/soc/intel/baytrail/baytrail/iomap.h
View File

@ -28,6 +28,7 @@
#define ILB_BASE_ADDRESS 0xfed08000 #define ILB_BASE_ADDRESS 0xfed08000
#define SPI_BASE_ADDRESS 0xfed01000 #define SPI_BASE_ADDRESS 0xfed01000
#define MPHY_BASE_ADDRESS 0xfef00000 #define MPHY_BASE_ADDRESS 0xfef00000
#define PUNIT_BASE_ADDRESS 0xfed05000
#define RCBA_BASE_ADDRESS 0xfed1c000 #define RCBA_BASE_ADDRESS 0xfed1c000
/* IO Port base */ /* IO Port base */

1
src/soc/intel/baytrail/baytrail/lpc.h
View File

@ -29,6 +29,7 @@
#define IBASE 0x50 #define IBASE 0x50
#define SBASE 0x54 #define SBASE 0x54
#define MPBASE 0x58 #define MPBASE 0x58
#define PUBASE 0x5c
#define UART_CONT 0x80 #define UART_CONT 0x80
#define RCBA 0xf0 #define RCBA 0xf0

2
src/soc/intel/baytrail/romstage/romstage.c
View File

@ -74,6 +74,8 @@ static void program_base_addresses(void)
pci_write_config32(lpc_dev, SBASE, reg); pci_write_config32(lpc_dev, SBASE, reg);
reg = MPHY_BASE_ADDRESS | 2; reg = MPHY_BASE_ADDRESS | 2;
pci_write_config32(lpc_dev, MPBASE, reg); pci_write_config32(lpc_dev, MPBASE, reg);
reg = PUNIT_BASE_ADDRESS | 2;
pci_write_config32(lpc_dev, PUBASE, reg);
reg = RCBA_BASE_ADDRESS | 1; reg = RCBA_BASE_ADDRESS | 1;
pci_write_config32(lpc_dev, RCBA, reg); pci_write_config32(lpc_dev, RCBA, reg);