soc/amd/morgana: Enable GPP clk req disabling
Enable GPP clk req disabling on morgana after reviewing against morgana ppr #57396, rev 1.52 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Id2502137486df7a8b0ac6a4b3e061b25b23e2e51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70465 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -8,6 +8,7 @@ romstage-y += port_descriptors.c
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ramstage-y += chromeos.c
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ramstage-y += gpio.c
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ramstage-y += port_descriptors.c
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ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_Updatable.bin),)
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APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_Updatable.bin
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@ -8,6 +8,7 @@ romstage-y += port_descriptors.c
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ramstage-y += chromeos.c
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ramstage-y += gpio.c
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ramstage-y += port_descriptors.c
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ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_Updatable.bin),)
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APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_Updatable.bin
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@ -61,9 +61,10 @@ config SOC_SPECIFIC_OPTIONS
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select SOC_AMD_COMMON_BLOCK_LPC # TODO: Check if this is still correct
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select SOC_AMD_COMMON_BLOCK_MCAX
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select SOC_AMD_COMMON_BLOCK_NONCAR
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select SOC_AMD_COMMON_BLOCK_PCI # TODO: Check if this is still correct
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select SOC_AMD_COMMON_BLOCK_PCI_MMCONF # TODO: Check if this is still correct
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select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER # TODO: Check if this is still correct
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select SOC_AMD_COMMON_BLOCK_PCI
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select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
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select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER
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select SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ
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select SOC_AMD_COMMON_BLOCK_PM
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select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE
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select SOC_AMD_COMMON_BLOCK_PSP_GEN2 # TODO: Check if this is still correct
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@ -7,6 +7,7 @@
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#include <amdblocks/chip.h>
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#include <amdblocks/i2c.h>
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#include <amdblocks/pci_clk_req.h>
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#include <gpio.h>
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#include <soc/i2c.h>
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#include <soc/southbridge.h>
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@ -92,11 +93,7 @@ struct soc_amd_morgana_config {
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/* The array index is the general purpose PCIe clock output number. Values in here
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aren't the values written to the register to have the default to be always on. */
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enum {
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GPP_CLK_ON, /* GPP clock always on; default */
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GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */
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GPP_CLK_OFF, /* GPP clk off */
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} gpp_clk_config[GPP_CLK_OUTPUT_AVAILABLE];
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enum gpp_clk_req gpp_clk_config[GPP_CLK_OUTPUT_AVAILABLE];
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/* performance policy for the PCIe links: power consumption vs. link speed */
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enum {
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@ -1,11 +1,10 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* TODO: Update for Morgana */
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#include <amdblocks/acpi.h>
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/amd_pci_util.h>
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#include <amdblocks/gpio.h>
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#include <amdblocks/pci_clk_req.h>
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#include <amdblocks/smi.h>
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#include <assert.h>
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#include <bootstate.h>
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@ -125,7 +124,7 @@ static void fch_init_acpi_ports(void)
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/* configure the general purpose PCIe clock outputs according to the devicetree settings */
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static void gpp_clk_setup(void)
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{
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const struct soc_amd_morgana_config *cfg = config_of_soc();
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struct soc_amd_morgana_config *cfg = config_of_soc();
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/* look-up table to be able to iterate over the PCIe clock output settings */
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const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = {
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@ -140,6 +139,8 @@ static void gpp_clk_setup(void)
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uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL);
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pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0],
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ARRAY_SIZE(cfg->gpp_clk_config));
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for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) {
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gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]);
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/*
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@ -1,7 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* TODO: Update for Morgana */
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#ifndef AMD_MORGANA_SOUTHBRIDGE_H
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#define AMD_MORGANA_SOUTHBRIDGE_H
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@ -13,7 +11,7 @@
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#define PM_PCI_CTRL 0x08
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#define FORCE_SLPSTATE_RETRY BIT(25)
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#define PWR_RESET_CFG 0x10
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#define TOGGLE_ALL_PWR_GOOD (1 << 1)
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#define TOGGLE_ALL_PWR_GOOD BIT(1)
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#define PM_SERIRQ_CONF 0x54
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#define PM_SERIRQ_NUM_BITS_17 0x0000
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#define PM_SERIRQ_NUM_BITS_18 0x0004
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@ -61,7 +59,6 @@
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#define PM_ACPI_SW_S5PWRMUX BIT(16)
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#define PM_ACPI_EN_SHUTDOWN_MSG BIT(17)
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#define PM_ACPI_EN_SYNC_FLOOD BIT(18)
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#define PM_ACPI_FORCE_SPIUSEPIN_0 BIT(19)
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#define PM_ACPI_EN_DF_INTRWAKE BIT(20)
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#define PM_ACPI_MASK_USB_S5_RST BIT(21)
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#define PM_ACPI_USE_RSMU_RESET BIT(22)
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@ -96,7 +93,7 @@
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#define GPP_CLK5_REQ_SHIFT 10
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#define GPP_CLK6_REQ_SHIFT 12
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#define GPP_CLK_OUTPUT_COUNT 7
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#define GPP_CLK_OUTPUT_AVAILABLE 4
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#define GPP_CLK_OUTPUT_AVAILABLE 7
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#define GPP_CLK_REQ_MASK(clk_shift) (0x3 << (clk_shift))
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#define GPP_CLK_REQ_ON(clk_shift) (0x3 << (clk_shift))
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#define GPP_CLK_REQ_EXT(clk_shift) (0x1 << (clk_shift))
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