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mainboard/ms7721: Copy files from "asus/f2a85-m" to "msi/ms7721". 

This patch adds a copy of the Asus F2A85-M code with only minimal changes.
(to ensure that the code compiles)

A second commit will be published to remove the copied code parts that
don't apply to the MS-7221 and to make everything else actually work
on the MS-7221 board.

Change-Id: I1426c0876c7bfeb264231c0d338301133c721484
Signed-off-by: Renze Nicolai <renze@rnplus.nl>
Reviewed-on: https://review.coreboot.org/17494
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Renze Nicolai 2016-11-18 23:08:13 +01:00 committed by Kyösti Mälkki
parent 809b5881a9
commit a688b7cb7b
26 changed files with 2441 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

103
src/mainboard/msi/ms7721/BiosCallOuts.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "AGESA.h"
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <cbfs.h>
#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h>
#include <stdlib.h>
static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr);
const BIOS_CALLOUT_STRUCT BiosCallouts[] =
{
{AGESA_DO_RESET, agesa_Reset },
{AGESA_READ_SPD, agesa_ReadSpd },
{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },
{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
{AGESA_FCH_OEM_CALLOUT, Fch_Oem_config },
{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }
};
const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
/**
* ASUS F2A85-M board ALC887-VD Verb Table
*
* Copied from `/sys/class/sound/hwC1D0/init_pin_configs` when running
* the vendor BIOS.
*/
const CODEC_ENTRY f2a85_m_alc887_VerbTbl[] = {
{0x11, 0x99430140},
{0x12, 0x411111f0},
{0x14, 0x01014010},
{0x15, 0x01011012},
{0x16, 0x01016011},
{0x17, 0x01012014},
{0x18, 0x01a19850},
{0x19, 0x02a19c60},
{0x1a, 0x0181305f},
{0x1b, 0x02214c20},
{0x1c, 0x411111f0},
{0x1d, 0x4005e601},
{0x1e, 0x01456130},
{0x1f, 0x411111f0},
{0xff, 0xffffffff}
};
static const CODEC_TBL_LIST CodecTableList[] =
{
{0x10ec0887, (CODEC_ENTRY*)&f2a85_m_alc887_VerbTbl[0]},
{(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
};
/**
* Fch Oem setting callback
*
* Configure platform specific Hudson device,
* such Azalia, SATA, GEC, IMC etc.
*/
static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
{
AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
if (StdHeader->Func == AMD_INIT_RESET) {
FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
FchParams_reset->FchReset.Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
} else if (StdHeader->Func == AMD_INIT_ENV) {
FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
/* Azalia Controller OEM Codec Table Pointer */
FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]);
/* Azalia Controller Front Panel OEM Table Pointer */
FchParams_env->Imc.ImcEnable = FALSE;
FchParams_env->Hwm.HwMonitorEnable = FALSE;
FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */
/* XHCI configuration */
FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
FchParams_env->Usb.Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
}
printk(BIOS_DEBUG, "Done\n");
return AGESA_SUCCESS;
}

81
src/mainboard/msi/ms7721/Kconfig Normal file
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#
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
# Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
if BOARD_MSI_MS7721
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_AMD_AGESA_FAMILY15_TN
select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
select SOUTHBRIDGE_AMD_AGESA_HUDSON
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select SUPERIO_ITE_IT8728F
select BOARD_ROMSIZE_KB_8192
select GFXUMA
select HUDSON_DISABLE_IMC
config MAINBOARD_DIR
string
default msi/ms7721
config MAINBOARD_PART_NUMBER
string
default "MS-7721"
config HW_MEM_HOLE_SIZEK
hex
default 0x200000
config MAX_CPUS
int
default 4
config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n
config HUDSON_XHCI_FWM
bool
default n
config HUDSON_IMC_FWM
bool
default n
config IRQ_SLOT_COUNT
int
default 11
config ONBOARD_VGA_IS_PRIMARY
bool
default y
config VGA_BIOS_ID
string
default "1002,9993"
config HUDSON_LEGACY_FREE
bool
default y
config POST_IO
bool
default n
endif # BOARD_MSI_MS7721

2
src/mainboard/msi/ms7721/Kconfig.name Normal file
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config BOARD_MSI_MS7721
bool "MS-7721 (FM2-A75MA-E35)"

22
src/mainboard/msi/ms7721/Makefile.inc Normal file
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#
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
romstage-y += buildOpts.c
romstage-y += BiosCallOuts.c
romstage-y += OemCustomize.c
ramstage-y += buildOpts.c
ramstage-y += BiosCallOuts.c
ramstage-y += OemCustomize.c

233
src/mainboard/msi/ms7721/OemCustomize.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "Porting.h"
#include "AGESA.h"
#include "amdlib.h"
#include <northbridge/amd/agesa/agesawrapper.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
#include <PlatformMemoryConfiguration.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
/*
* Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)
*
* Lane Id
* 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8
* 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8
* 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8
* 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8
* 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7
* 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7
* 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7
* 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7
* 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI
* 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI
* 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI
* 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI
* 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI
* 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI
* 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI
* 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI
* 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI
* 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI
* 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI
* 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI
* 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI
* 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI
* 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI
* 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI
* 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs)
* 25 DP0_TX[P,N]1
* 26 DP0_TX[P,N]2
* 27 DP0_TX[P,N]3
* 28 DP1_TX[P,N]0
* 29 DP1_TX[P,N]1
* 30 DP1_TX[P,N]2
* 31 DP1_TX[P,N]3
* 32 DP2_TX[P,N]0
* 33 DP2_TX[P,N]1
* 34 DP2_TX[P,N]2
* 35 DP2_TX[P,N]3
* 36 DP2_TX[P,N]4
* 37 DP2_TX[P,N]5
* 38 DP2_TX[P,N]6
*/
static const PCIe_PORT_DESCRIPTOR PortList [] = {
/* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
},
/* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
},
/* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */
{
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
},
};
/*
* It is not known, if the setup is complete.
*
* Tested and works: VGA/DVI
* Untested: HDMI
*/
static const PCIe_DDI_DESCRIPTOR DdiList [] = {
// DP0 to HDMI0/DP
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1)
},
// DP1 to FCH
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
},
// DP2 to HDMI1/DP
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux3, Hdp3)
},
};
static const PCIe_COMPLEX_DESCRIPTOR Trinity = {
DESCRIPTOR_TERMINATE_LIST,
0,
&PortList[0],
&DdiList[0]
};
/*---------------------------------------------------------------------------------------*/
/**
* OemCustomizeInitEarly
*
* Description:
* This stub function will call the host environment through the binary block
* interface (call-out port) to provide a user hook opportunity
*
* Parameters:
* @param[in] *InitEarly
*
* @retval VOID
*
**/
/*---------------------------------------------------------------------------------------*/
static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
{
AGESA_STATUS Status;
VOID *TrinityPcieComplexListPtr;
VOID *TrinityPciePortPtr;
VOID *TrinityPcieDdiPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
// GNB PCIe topology Porting
//
// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
//
AllocHeapParams.RequestedBufferSize = sizeof(Trinity) + sizeof(PortList) + sizeof(DdiList);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
ASSERT(Status == AGESA_SUCCESS);
TrinityPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(Trinity);
TrinityPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(PortList);
TrinityPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemFill (TrinityPcieComplexListPtr,
0,
sizeof(Trinity),
&InitEarly->StdHeader);
LibAmdMemFill (TrinityPciePortPtr,
0,
sizeof(PortList),
&InitEarly->StdHeader);
LibAmdMemFill (TrinityPcieDdiPtr,
0,
sizeof(DdiList),
&InitEarly->StdHeader);
LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof(Trinity), &InitEarly->StdHeader);
LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader);
LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader);
((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr;
((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr;
InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr;
return AGESA_SUCCESS;
}
static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
{
/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------
* CUSTOMER OVERIDES MEMORY TABLE
*----------------------------------------------------------------------------------------
*/
#if IS_ENABLED(CONFIG_BOARD_MSI_MS7721)
/*
* Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
* (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
/*
TODO: is this OK for DDR3 socket FM2?
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
*/
PSO_END
};
#endif /* CONFIG_BOARD_MSI_MS7721 */
const struct OEM_HOOK OemCustomize = {
.InitEarly = OemInitEarly,
.InitMid = OemInitMid,
};

59
src/mainboard/msi/ms7721/OptionsIds.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/**
* @file
*
* IDS Option File
*
* This file is used to switch on/off IDS features.
*
*/
#ifndef _OPTION_IDS_H_
#define _OPTION_IDS_H_
/**
*
* This file generates the defaults tables for the Integrated Debug Support
* Module. The documented build options are imported from a user controlled
* file for processing. The build options for the Integrated Debug Support
* Module are listed below:
*
* IDSOPT_IDS_ENABLED
* IDSOPT_ERROR_TRAP_ENABLED
* IDSOPT_CONTROL_ENABLED
* IDSOPT_TRACING_ENABLED
* IDSOPT_PERF_ANALYSIS
* IDSOPT_ASSERT_ENABLED
* IDS_DEBUG_PORT
* IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
*
**/
//#define IDSOPT_IDS_ENABLED TRUE
//#define IDSOPT_CONTROL_ENABLED TRUE
#define IDSOPT_TRACING_ENABLED TRUE
#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
//#define IDSOPT_PERF_ANALYSIS TRUE
#define IDSOPT_ASSERT_ENABLED TRUE
//#undef IDSOPT_DEBUG_ENABLED
//#define IDSOPT_DEBUG_ENABLED FALSE
//#undef IDSOPT_HOST_SIMNOW
//#define IDSOPT_HOST_SIMNOW FALSE
//#undef IDSOPT_HOST_HDT
//#define IDSOPT_HOST_HDT FALSE
//#define IDS_DEBUG_PORT 0x80
#endif

97
src/mainboard/msi/ms7721/acpi/AmdImc.asl Normal file
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//BTDC Due to IMC Fan, ACPI control codes
OperationRegion(IMIO, SystemIO, 0x3E, 0x02)
Field(IMIO , ByteAcc, NoLock, Preserve) {
IMCX,8,
IMCA,8
}
IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) {
Offset(0x80),
MSTI, 8,
MITS, 8,
MRG0, 8,
MRG1, 8,
MRG2, 8,
MRG3, 8,
}
Method(WACK, 0)
{
Store(0, Local0)
Store(50, Local1)
While (LAnd (LNotEqual(Local0, 0xFA), LGreater(Local1,0))) {
Store(MRG0, Local0)
Sleep(10)
Decrement(Local1)
}
}
//Init
Method (ITZE, 0)
{
Store(0, MRG0)
Store(0xB5, MRG1)
Store(0, MRG2)
Store(0x96, MSTI)
WACK()
Store(0, MRG0)
Store(0, MRG1)
Store(0, MRG2)
Store(0x80, MSTI)
WACK()
Or(MRG2, 0x01, Local0)
Store(0, MRG0)
Store(0, MRG1)
Store(Local0, MRG2)
Store(0x81, MSTI)
WACK()
}
//Sleep
Method (IMSP, 0)
{
Store(0, MRG0)
Store(0xB5, MRG1)
Store(0, MRG2)
Store(0x96, MSTI)
WACK()
Store(0, MRG0)
Store(1, MRG1)
Store(0, MRG2)
Store(0x98, MSTI)
WACK()
Store(0, MRG0)
Store(0xB4, MRG1)
Store(0, MRG2)
Store(0x96, MSTI)
WACK()
}
//Wake
Method (IMWK, 0)
{
Store(0, MRG0)
Store(0xB5, MRG1)
Store(0, MRG2)
Store(0x96, MSTI)
WACK()
Store(0, MRG0)
Store(0, MRG1)
Store(0, MRG2)
Store(0x80, MSTI)
WACK()
Or(MRG2, 0x01, Local0)
Store(0, MRG0)
Store(0, MRG1)
Store(Local0, MRG2)
Store(0x81, MSTI)
WACK()
}

111
src/mainboard/msi/ms7721/acpi/cpstate.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* This file defines the processor and performance state capability
* for each core in the system. It is included into the DSDT for each
* core. It assumes that each core of the system has the same performance
* characteristics.
*/
/*
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
{
Scope (\_PR) {
Processor(CPU0,0,0x808,0x06) {
#include "cpstate.asl"
}
Processor(CPU1,1,0x0,0x0) {
#include "cpstate.asl"
}
Processor(CPU2,2,0x0,0x0) {
#include "cpstate.asl"
}
Processor(CPU3,3,0x0,0x0) {
#include "cpstate.asl"
}
}
*/
/* P-state support: The maximum number of P-states supported by the */
/* CPUs we'll use is 6. */
/* Get from AMI BIOS. */
Name(_PSS, Package(){
Package()
{
0x00000D48,
0x00011170,
0x00000004,
0x00000004,
0x00000000,
0x00000000
},
Package()
{
0x00000AF0,
0x0000C544,
0x00000004,
0x00000004,
0x00000001,
0x00000001
},
Package()
{
0x000009C4,
0x0000B3B0,
0x00000004,
0x00000004,
0x00000002,
0x00000002
},
Package()
{
0x00000898,
0x0000ABE0,
0x00000004,
0x00000004,
0x00000003,
0x00000003
},
Package()
{
0x00000708,
0x0000A410,
0x00000004,
0x00000004,
0x00000004,
0x00000004
},
Package()
{
0x00000578,
0x00006F54,
0x00000004,
0x00000004,
0x00000005,
0x00000005
}
})
Name(_PCT, Package(){
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
})
Method(_PPC, 0){
Return(0)
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
Scope(\_GPE) { /* Start Scope GPE */
/* General event 3 */
Method(_L03) {
/* DBGO("\\_GPE\\_L00\n") */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
/* Legacy PM event */
Method(_L08) {
/* DBGO("\\_GPE\\_L08\n") */
}
/* Temp warning (TWarn) event */
Method(_L09) {
/* DBGO("\\_GPE\\_L09\n") */
/* Notify (\_TZ.TZ00, 0x80) */
}
/* USB controller PME# */
Method(_L0B) {
/* DBGO("\\_GPE\\_L0B\n") */
Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
/* ExtEvent0 SCI event */
Method(_L10) {
/* DBGO("\\_GPE\\_L10\n") */
}
/* ExtEvent1 SCI event */
Method(_L11) {
/* DBGO("\\_GPE\\_L11\n") */
}
/* GPIO0 or GEvent8 event */
Method(_L18) {
/* DBGO("\\_GPE\\_L18\n") */
Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
/* Azalia SCI event */
Method(_L1B) {
/* DBGO("\\_GPE\\_L1B\n") */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
} /* End Scope GPE */

32
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* Data to be patched by the BIOS during POST */
/* FIXME the patching is not done yet! */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */
Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
Name(OSV, Ones) /* Assume nothing */
Name(PMOD, One) /* Assume APIC */

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* Routing is in System Bus scope */
Name(PR0, Package(){
/* NB devices */
/* Bus 0, Dev 0 - F15 Host Controller */
Package(){0x0000FFFF, 0, INTA, 0 },
Package(){0x0000FFFF, 1, INTB, 0 },
Package(){0x0000FFFF, 2, INTC, 0 },
Package(){0x0000FFFF, 3, INTD, 0 },
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
Package(){0x0001FFFF, 0, INTB, 0 },
Package(){0x0001FFFF, 1, INTC, 0 },
/* Bus 0, Dev 2 - PCIe Bridge for x16 slot */
Package(){0x0002FFFF, 0, INTC, 0 },
Package(){0x0002FFFF, 1, INTD, 0 },
Package(){0x0002FFFF, 2, INTA, 0 },
Package(){0x0002FFFF, 3, INTB, 0 },
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
/* Bus 0, Dev 4 - PCIe Bridge for 4x slot */
Package(){0x0004FFFF, 0, INTA, 0 },
Package(){0x0004FFFF, 1, INTB, 0 },
Package(){0x0004FFFF, 2, INTC, 0 },
Package(){0x0004FFFF, 3, INTD, 0 },
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
/* Bus 0, Dev 8 - Southbridge port (normally hidden) */
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
Package(){0x0014FFFF, 0, INTA, 0 },
Package(){0x0014FFFF, 1, INTB, 0 },
Package(){0x0014FFFF, 2, INTC, 0 },
Package(){0x0014FFFF, 3, INTD, 0 },
/* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
* EHCI @ func 2 */
Package(){0x0012FFFF, 0, INTC, 0 },
Package(){0x0012FFFF, 1, INTB, 0 },
Package(){0x0013FFFF, 0, INTC, 0 },
Package(){0x0013FFFF, 1, INTB, 0 },
Package(){0x0016FFFF, 0, INTC, 0 },
Package(){0x0016FFFF, 1, INTB, 0 },
/* SB devices */
/* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
Package(){0x0010FFFF, 0, INTC, 0 },
Package(){0x0010FFFF, 1, INTB, 0 },
/* Bus 0, Dev 17 - SATA controller */
Package(){0x0011FFFF, 0, INTD, 0 },
/* Bus 0, Dev 21 Pcie Bridge */
Package(){0x0015FFFF, 0, INTA, 0 },
Package(){0x0015FFFF, 1, INTB, 0 },
Package(){0x0015FFFF, 2, INTC, 0 },
Package(){0x0015FFFF, 3, INTD, 0 },
})
Name(APR0, Package(){
/* NB devices in APIC mode */
/* Bus 0, Dev 0 - F15 Host Controller */
Package(){0x0000FFFF, 0, 0, 16 },
Package(){0x0000FFFF, 1, 0, 17 },
Package(){0x0000FFFF, 2, 0, 18 },
Package(){0x0000FFFF, 3, 0, 19 },
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
Package(){0x0001FFFF, 0, 0, 17 },
Package(){0x0001FFFF, 1, 0, 18 },
/* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */
Package(){0x0002FFFF, 0, 0, 18 },
Package(){0x0002FFFF, 1, 0, 19 },
Package(){0x0002FFFF, 2, 0, 16 },
Package(){0x0002FFFF, 3, 0, 17 },
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
/* Bus 0, Dev 4 - PCIe Bridge for x4 PCIe Slot black */
Package(){0x0004FFFF, 0, 0, 16 },
Package(){0x0004FFFF, 1, 0, 17 },
Package(){0x0004FFFF, 2, 0, 18 },
Package(){0x0004FFFF, 3, 0, 19 },
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
/* Bus 0, Dev 7 - PCIe Bridge for network card */
/* Bus 0, Dev 8 - Southbridge port (normally hidden) */
/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
Package(){0x0014FFFF, 0, 0, 16 },
Package(){0x0014FFFF, 1, 0, 17 },
Package(){0x0014FFFF, 2, 0, 18 },
Package(){0x0014FFFF, 3, 0, 19 },
/* SB devices in APIC mode */
/* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
* EHCI @ func 2 */
Package(){0x0012FFFF, 0, 0, 18 },
Package(){0x0012FFFF, 1, 0, 17 },
Package(){0x0013FFFF, 0, 0, 18 },
Package(){0x0013FFFF, 1, 0, 17 },
Package(){0x0016FFFF, 0, 0, 18 },
Package(){0x0016FFFF, 1, 0, 17 },
/* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
Package(){0x0010FFFF, 0, 0, 0x12},
Package(){0x0010FFFF, 1, 0, 0x11},
/* Bus 0, Dev 17 - SATA controller */
Package(){0x0011FFFF, 0, 0, 19 },
/* Bus 0, Dev 21 PCIE Bridge */
Package(){0x0015FFFF, 0, 0, 17 },
Package(){0x0015FFFF, 1, 0, 18 },
Package(){0x0015FFFF, 2, 0, 19 },
Package(){0x0015FFFF, 3, 0, 16 },
})
Name(PS2, Package(){
/* The external GFX - Hooked to PCIe slot 2 */
Package(){0x0000FFFF, 0, INTD, 0 },
Package(){0x0000FFFF, 1, INTA, 0 },
Package(){0x0000FFFF, 2, INTB, 0 },
Package(){0x0000FFFF, 3, INTC, 0 },
})
Name(APS2, Package(){
/* The external GFX - Hooked to PCIe slot 2 */
Package(){0x0000FFFF, 0, 0, 18 },
Package(){0x0000FFFF, 1, 0, 19 },
Package(){0x0000FFFF, 2, 0, 16 },
Package(){0x0000FFFF, 3, 0, 17 },
})
/* black slot */
Name(PS4, Package(){
/* PCIe slot - Hooked to PCIe slot 4 */
Package(){0x0000FFFF, 0, INTA, 0 },
Package(){0x0000FFFF, 1, INTB, 0 },
Package(){0x0000FFFF, 2, INTC, 0 },
Package(){0x0000FFFF, 3, INTD, 0 },
})
Name(APS4, Package(){
/* PCIe slot - Hooked to PCIe slot 4 */
Package(){0x0000FFFF, 0, 0, 16 },
Package(){0x0000FFFF, 1, 0, 17 },
Package(){0x0000FFFF, 2, 0, 18 },
Package(){0x0000FFFF, 3, 0, 19 },
})
Name(PS5, Package(){
/* PCIe slot - Hooked to PCIe slot 5 */
Package(){0x0000FFFF, 0, INTB, 0 },
Package(){0x0000FFFF, 1, INTC, 0 },
Package(){0x0000FFFF, 2, INTD, 0 },
Package(){0x0000FFFF, 3, INTA, 0 },
})
Name(APS5, Package(){
/* PCIe slot - Hooked to PCIe slot 5 */
Package(){0x0000FFFF, 0, 0, 17 },
Package(){0x0000FFFF, 1, 0, 18 },
Package(){0x0000FFFF, 2, 0, 19 },
Package(){0x0000FFFF, 3, 0, 16 },
})
Name(PS6, Package(){
/* PCIe slot - Hooked to PCIe slot 6 */
Package(){0x0000FFFF, 0, INTC, 0 },
Package(){0x0000FFFF, 1, INTD, 0 },
Package(){0x0000FFFF, 2, INTA, 0 },
Package(){0x0000FFFF, 3, INTB, 0 },
})
Name(APS6, Package(){
/* PCIe slot - Hooked to PCIe slot 6 */
Package(){0x0000FFFF, 0, 0, 18 },
Package(){0x0000FFFF, 1, 0, 19 },
Package(){0x0000FFFF, 2, 0, 16 },
Package(){0x0000FFFF, 3, 0, 17 },
})
Name(PS7, Package(){
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
Package(){0x0000FFFF, 0, INTD, 0 },
Package(){0x0000FFFF, 1, INTA, 0 },
Package(){0x0000FFFF, 2, INTB, 0 },
Package(){0x0000FFFF, 3, INTC, 0 },
})
Name(APS7, Package(){
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
Package(){0x0000FFFF, 0, 0, 19 },
Package(){0x0000FFFF, 1, 0, 16 },
Package(){0x0000FFFF, 2, 0, 17 },
Package(){0x0000FFFF, 3, 0, 18 },
})
Name(PBR0, Package(){
/* PCIx1 on SB */
Package(){0x0000FFFF, 0, INTA, 0 },
Package(){0x0000FFFF, 1, INTB, 0 },
Package(){0x0000FFFF, 2, INTC, 0 },
Package(){0x0000FFFF, 3, INTD, 0 },
})
Name(ABR0, Package(){
/* PCIx1 on SB */
Package(){0x0000FFFF, 0, 0, 0x10 },
Package(){0x0000FFFF, 1, 0, 0x11 },
Package(){0x0000FFFF, 2, 0, 0x12 },
Package(){0x0000FFFF, 3, 0, 0x13 },
})
Name(PBR1, Package(){
/* Onboard network */
Package(){0x0000FFFF, 0, INTB, 0 },
Package(){0x0000FFFF, 1, INTC, 0 },
Package(){0x0000FFFF, 2, INTD, 0 },
Package(){0x0000FFFF, 3, INTA, 0 },
})
Name(ABR1, Package(){
/* Onboard network */
Package(){0x0000FFFF, 0, 0, 0x11 },
Package(){0x0000FFFF, 1, 0, 0x12 },
Package(){0x0000FFFF, 2, 0, 0x13 },
Package(){0x0000FFFF, 3, 0, 0x10 },
})
/* SB PCI Bridge */
Name(PCIB, Package(){
/* PCI slots: slot 0 behind Dev14, Fun4. */
Package(){0x0005FFFF, 0, 0, 0x14 },
Package(){0x0005FFFF, 1, 0, 0x15 },
Package(){0x0005FFFF, 2, 0, 0x16 },
Package(){0x0005FFFF, 3, 0, 0x17 },
})

16
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* No SATA functionality */

22
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
Scope(\_SI) {
Method(_SST, 1) {
/* DBGO("\\_SI\\_SST\n") */
/* DBGO(" New Indicator state: ") */
/* DBGO(Arg0) */
/* DBGO("\n") */
}
} /* End Scope SI */

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* Wake status package */
Name(WKST,Package(){Zero, Zero})
/*
* \_PTS - Prepare to Sleep method
*
* Entry:
* Arg0=The value of the sleeping state S1=1, S2=2, etc
*
* Exit:
* -none-
*
* The _PTS control method is executed at the beginning of the sleep process
* for S1-S5. The sleeping value is passed to the _PTS control method. This
* control method may be executed a relatively long time before entering the
* sleep state and the OS may abort the operation without notification to
* the ACPI driver. This method cannot modify the configuration or power
* state of any device in the system.
*/
Method(\_PTS, 1) {
/* DBGO("\\_PTS\n") */
/* DBGO("From S0 to S") */
/* DBGO(Arg0) */
/* DBGO("\n") */
/* Clear sleep SMI status flag and enable sleep SMI trap. */
/*Store(One, CSSM)
Store(One, SSEN)*/
/* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\_SB.SBRI, 0x13)) {
* Store(0,\_SB.PWDE)
*}
*/
/* Clear wake status structure. */
Store(0, Index(WKST,0))
Store(0, Index(WKST,1))
Store (0x07, UPWS)
} /* End Method(\_PTS) */
/*
* \_BFS OEM Back From Sleep method
*
* Entry:
* Arg0=The value of the sleeping state S1=1, S2=2
*
* Exit:
* -none-
*/
Method(\_BFS, 1) {
/* DBGO("\\_BFS\n") */
/* DBGO("From S") */
/* DBGO(Arg0) */
/* DBGO(" to S0\n") */
}
/*
* \_WAK System Wake method
*
* Entry:
* Arg0=The value of the sleeping state S1=1, S2=2
*
* Exit:
* Return package of 2 DWords
* Dword 1 - Status
* 0x00000000 wake succeeded
* 0x00000001 Wake was signaled but failed due to lack of power
* 0x00000002 Wake was signaled but failed due to thermal condition
* Dword 2 - Power Supply state
* if non-zero the effective S-state the power supply entered
*/
Method(\_WAK, 1) {
/* DBGO("\\_WAK\n") */
/* DBGO("From S") */
/* DBGO(Arg0) */
/* DBGO(" to S0\n") */
Return(WKST)
} /* End Method(\_WAK) */

16
src/mainboard/msi/ms7721/acpi/superio.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* No Super I/O device or functionality yet */

16
src/mainboard/msi/ms7721/acpi/thermal.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* No thermal zone functionality */

50
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <northbridge/amd/agesa/agesawrapper.h>
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <arch/ioapic.h>
#include <console/console.h>
#include <cpu/amd/amdfam15.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <string.h>
unsigned long acpi_fill_madt(unsigned long current)
{
/* create all subtables for processors */
current = acpi_create_madt_lapics(current);
/* Write Hudson IOAPIC, only one */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 0, 2, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 9, 9, 0xF);
/* 0: mean bus 0--->ISA */
/* 0: PIC 0 */
/* 2: APIC 2 */
/* 5 mean: 0101 --> Edge-triggered, Active high */
/* create all subtables for processors */
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
/* 1: LINT1 connect to NMI */
return current;
}

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Category: desktop
Board URL: https://www.msi.com/Motherboard/FM2-A75MA-E35.html
ROM package: SOIC8
ROM protocol: SPI
ROM socketed: n
Flashrom support: y
Release year: 2012

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/**
* @file
*
* AMD User options selection for a Brazos platform solution system
*
* This file is placed in the user's platform directory and contains the
* build option selections desired for that platform.
*
* For Information about this file, see @ref platforminstall.
*
*/
#include <stdlib.h>
#include <vendorcode/amd/agesa/f15tn/AGESA.h>
/* Include the files that instantiate the configuration definitions. */
#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
/* the next two headers depend on heapManager.h */
#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h>
/* These tables are optional and may be used to adjust memory timing settings */
#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>
#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
#define INSTALL_FAMILY_14_SUPPORT FALSE
#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
/* Select the CPU socket type. */
#define INSTALL_G34_SOCKET_SUPPORT FALSE
#define INSTALL_C32_SOCKET_SUPPORT FALSE
#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
#define INSTALL_FS1_SOCKET_SUPPORT FALSE
#define INSTALL_FM1_SOCKET_SUPPORT FALSE
#define INSTALL_FP2_SOCKET_SUPPORT FALSE
#define INSTALL_FT1_SOCKET_SUPPORT FALSE
#define INSTALL_AM3_SOCKET_SUPPORT FALSE
#define INSTALL_FM2_SOCKET_SUPPORT TRUE
//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE
#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
#define BLDOPT_REMOVE_SRAT FALSE //TRUE
#define BLDOPT_REMOVE_SLIT FALSE //TRUE
#define BLDOPT_REMOVE_WHEA FALSE //TRUE
#define BLDOPT_REMOVE_CRAT TRUE
#define BLDOPT_REMOVE_DMI TRUE
//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
//This element selects whether P-States should be forced to be independent,
// as reported by the ACPI _PSD object. For single-link processors,
// setting TRUE for OS to support this feature.
//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE
#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
/* Build configuration values here.
*/
#define BLDCFG_VRM_CURRENT_LIMIT 90000
#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0
#define BLDCFG_PLAT_NUM_IO_APICS 3
#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
#define BLDCFG_MEM_INIT_PSTATE 0
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE
#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE
#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
#define BLDCFG_MEMORY_POWER_DOWN TRUE
#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
#define BLDCFG_ONLINE_SPARE FALSE
#define BLDCFG_BANK_SWIZZLE TRUE
#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY
#define BLDCFG_DQS_TRAINING_CONTROL TRUE
#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
#define BLDCFG_USE_BURST_MODE FALSE
#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
#define BLDCFG_ENABLE_ECC_FEATURE FALSE
#define BLDCFG_ECC_REDIRECTION FALSE
#define BLDCFG_SCRUB_DRAM_RATE 0
#define BLDCFG_SCRUB_L2_RATE 0
#define BLDCFG_SCRUB_L3_RATE 0
#define BLDCFG_SCRUB_IC_RATE 0
#define BLDCFG_SCRUB_DC_RATE 0
#define BLDCFG_ECC_SYMBOL_SIZE 4
#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
#define BLDCFG_ECC_SYNC_FLOOD FALSE
#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
#define BLDCFG_1GB_ALIGN FALSE
#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36%
#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770
#define BLDOPT_REMOVE_ALIB FALSE
#define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled
#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P'
#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200
#define BLDCFG_CFG_ABM_SUPPORT 0
//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
// Specify the default values for the VRM controlling the VDDNB plane.
// If not specified, the values used for the core VRM will be applied
//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity
//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L
//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime
//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity
//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity
//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity
#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000
#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
#if CONFIG_GFXUMA
#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M
#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
#endif
#define BLDCFG_IOMMU_SUPPORT TRUE
#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
/* Process the options...
* This file include MUST occur AFTER the user option selection settings
*/
/*
* Customized OEM build configurations for FCH component
*/
// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00
// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20
// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00
// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420
// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000
// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000
// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000
// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0
// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00
// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000
// #define BLDCFG_AZALIA_SSID 0x780D1022
// #define BLDCFG_SMBUS_SSID 0x780B1022
// #define BLDCFG_IDE_SSID 0x780C1022
// #define BLDCFG_SATA_AHCI_SSID 0x78011022
// #define BLDCFG_SATA_IDE_SSID 0x78001022
// #define BLDCFG_SATA_RAID5_SSID 0x78031022
// #define BLDCFG_SATA_RAID_SSID 0x78021022
// #define BLDCFG_EHCI_SSID 0x78081022
// #define BLDCFG_OHCI_SSID 0x78071022
// #define BLDCFG_LPC_SSID 0x780E1022
// #define BLDCFG_SD_SSID 0x78061022
// #define BLDCFG_XHCI_SSID 0x78121022
// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE
// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4
// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE
// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE
// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE
// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE
// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE
// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE
// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
{
{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
{ AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
{ AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
{ AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
{ CPU_LIST_TERMINAL }
};
#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
// This is the delivery package title, "BrazosPI"
// This string MUST be exactly 8 characters long
#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
// This is the release version number of the AGESA component
// This string MUST be exactly 12 characters long
#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
/* MEMORY_BUS_SPEED */
#define DDR400_FREQUENCY 200 ///< DDR 400
#define DDR533_FREQUENCY 266 ///< DDR 533
#define DDR667_FREQUENCY 333 ///< DDR 667
#define DDR800_FREQUENCY 400 ///< DDR 800
#define DDR1066_FREQUENCY 533 ///< DDR 1066
#define DDR1333_FREQUENCY 667 ///< DDR 1333
#define DDR1600_FREQUENCY 800 ///< DDR 1600
#define DDR1866_FREQUENCY 933 ///< DDR 1866
#define DDR2100_FREQUENCY 1050 ///< DDR 2100
#define DDR2133_FREQUENCY 1066 ///< DDR 2133
#define DDR2400_FREQUENCY 1200 ///< DDR 2400
#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
/* QUANDRANK_TYPE*/
#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
/* USER_MEMORY_TIMING_MODE */
#define TIMING_MODE_AUTO 0 ///< Use best rate possible
#define TIMING_MODE_LIMITED 1 ///< Set user top limit
#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
/* POWER_DOWN_MODE */
#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
/*
* Agesa optional capabilities selection.
* Uncomment and mark FALSE those features you wish to include in the build.
* Comment out or mark TRUE those features you want to REMOVE from the build.
*/
#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
/* The AGESA likes to enable 512 bytes region on this base for LPC bus */
#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800
#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804
#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808
#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810
#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820
#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0
#define DFLT_HPET_BASE_ADDRESS 0xFED00000
#define DFLT_SMI_CMD_PORT 0xB0
#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
#define DFLT_GEC_BASE_ADDRESS 0xFED61000
#define DFLT_AZALIA_SSID 0x780D1022
#define DFLT_SMBUS_SSID 0x780B1022
#define DFLT_IDE_SSID 0x780C1022
#define DFLT_SATA_AHCI_SSID 0x78011022
#define DFLT_SATA_IDE_SSID 0x78001022
#define DFLT_SATA_RAID5_SSID 0x78031022
#define DFLT_SATA_RAID_SSID 0x78021022
#define DFLT_EHCI_SSID 0x78081022
#define DFLT_OHCI_SSID 0x78071022
#define DFLT_LPC_SSID 0x780E1022
#define DFLT_SD_SSID 0x78061022
#define DFLT_XHCI_SSID 0x78121022
#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE
#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
#define DFLT_FCH_GPP_LINK_CONFIG PortA1B1C1D1
#define DFLT_FCH_GPP_PORT0_PRESENT TRUE
#define DFLT_FCH_GPP_PORT1_PRESENT TRUE
#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
//#define BLDCFG_IR_PIN_CONTROL 0x33
//#define FCH_NO_XHCI_SUPPORT FALSE
GPIO_CONTROL f2a85_m_gpio[] = {
// {183, Function1, PullUpB},
{-1}
};
#define BLDCFG_FCH_GPIO_CONTROL_LIST (&f2a85_m_gpio[0])
// The following definitions specify the default values for various parameters in which there are
// no clearly defined defaults to be used in the common file. The values below are based on product
// and BKDG content, please consult the AGESA Memory team for consultation.
#define DFLT_SCRUB_DRAM_RATE (0)
#define DFLT_SCRUB_L2_RATE (0)
#define DFLT_SCRUB_L3_RATE (0)
#define DFLT_SCRUB_IC_RATE (0)
#define DFLT_SCRUB_DC_RATE (0)
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
#define DFLT_VRM_SLEW_RATE (5000)
/* Moving this include up will break AGESA. */
#include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h>

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src/mainboard/msi/ms7721/cmos.layout Normal file
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#*****************************************************************************
#
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#*****************************************************************************
entries
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
392 3 e 5 baud_rate
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
456 1 e 1 ECC_memory
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
5 0 115200
5 1 57600
5 2 38400
5 3 19200
5 4 9600
5 5 4800
5 6 2400
5 7 1200
6 6 Notice
6 7 Info
6 8 Debug
6 9 Spew
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
checksums
checksum 392 983 984

133
src/mainboard/msi/ms7721/devicetree.cb Normal file
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#
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
chip northbridge/amd/agesa/family15tn/root_complex
device cpu_cluster 0 on
chip cpu/amd/agesa/family15tn
device lapic 10 on end
end
end
device domain 0 on
subsystemid 0x1022 0x1410 inherit
chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
device pci 0.0 on end # Root Complex
device pci 0.2 on end # IOMMU
device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX
device pci 1.1 on end # Internal Multimedia
device pci 2.0 on end # PCIE SLOT0 x16 blue
device pci 3.0 off end # unused?
device pci 4.0 on end # PCIE 4x black
device pci 5.0 off end # unused?
device pci 6.0 off end # unused?
device pci 7.0 off end # LAN
device pci 8.0 off end # NB/SB Link P2P bridge
end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
device pci 10.0 on end # XHCI HC0
device pci 10.1 on end # XHCI HC1
device pci 11.0 on end # SATA
device pci 12.0 on end # USB
device pci 12.2 on end # USB
device pci 13.0 on end # USB
device pci 13.2 on end # USB
device pci 14.0 on # SMBUS
chip drivers/generic/generic #dimm 0
device i2c 50 on end # 7-bit SPD address
end
chip drivers/generic/generic #dimm 1
device i2c 51 on end # 7-bit SPD address
end
end # SM
device pci 14.1 off end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
chip superio/ite/it8728f
register hwm_ctl_register = "0xc0"
register hwm_main_ctl_register = "0x33"
register hwm_adc_temp_chan_en_reg = "0x38"
register hwm_fan1_ctl_pwm = "0x00"
register hwm_fan2_ctl_pwm = "0x00"
register hwm_fan3_ctl_pwm = "0x00"
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.2 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.3 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.4 on # Env Controller
io 0x60 = 0x290
io 0x62 = 0x220
irq 0x70 = 0
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
end
device pnp 2e.6 off # Mouse
irq 0x70 = 12
end
device pnp 2e.7 on # GPIO
io 0x60 = 0x228 #SMI
io 0x62 = 0x300 #Simple I/O
io 0x64 = 0x238 #Phony resource IT8603E does not have it
irq 0x70 = 0
end
device pnp 2e.a off end # CIR
end #superio/ite/it8728f
end #device pci 14.3 # LPC
device pci 14.4 on end # PCI 0x4384
device pci 14.5 on end # USB 2
device pci 14.6 off end # Gec
device pci 14.7 off end # SD
device pci 15.0 on end # PCIe 0 - onboard PCIe 1x
device pci 15.1 on end # PCIe 1 onboard gigabit
device pci 15.2 off end # unused
device pci 15.3 off end # unused
end #chip southbridge/amd/hudson
device pci 18.0 on end
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
device pci 18.4 on end
device pci 18.5 on end
register "spdAddrLookup" = "
{
{ {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
}"
end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
end #domain
end #chip northbridge/amd/agesa/family15tn/root_complex

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src/mainboard/msi/ms7721/dsdt.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* DefinitionBlock Statement */
DefinitionBlock (
"DSDT.AML", /* Output filename */
"DSDT", /* Signature */
0x02, /* DSDT Revision, needs to be 2 for 64bit */
"ASUS ", /* OEMID */
"COREBOOT", /* TABLE ID */
0x00010001 /* OEM Revision */
)
{ /* Start of ASL file */
/* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
/* Globals for the platform */
#include "acpi/mainboard.asl"
/* PCI IRQ mapping for the Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
/* Describe the processor tree (\_PR) */
#include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
/* Describe the supported Sleep States for this Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/sleepstates.asl>
/* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */
#include "acpi/sleep.asl"
Scope(\_SB) {
/* global utility methods expected within the \_SB scope */
#include <arch/x86/acpi/globutil.asl>
/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
#include "acpi/routing.asl"
Device(PWRB) {
Name(_HID, EISAID("PNP0C0C"))
Name(_UID, 0xAA)
Name(_PRW, Package () {3, 0x04})
Name(_STA, 0x0B)
}
Device(PCI0) {
/* Describe the AMD Northbridge */
#include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl>
/* Describe the AMD Fusion Controller Hub Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/fch.asl>
/**
* TODO: The devices listed here (SBR0 and SBR1) do not appear to
* be referenced anywhere and could possibly be removed.
*/
Device(SBR0) { /* PCIe 1x SB */
Name(_ADR, 0x00150000)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
If(PMOD){ Return(ABR0) } /* APIC mode */
Return (PBR0) /* PIC mode */
}
}
Device(SBR1) { /* Onboard network */
Name(_ADR, 0x00150001)
Name(_PRW, Package() {0x18, 4})
Method(_PRT, 0) {
If(PMOD){ Return(ABR1) } /* APIC mode */
Return (PBR1) /* PIC mode */
}
}
}
/* Describe PCI INT[A-H] for the Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
} /* End Scope(_SB) */
/* Describe SMBUS for the Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
/* Define the General Purpose Events for the platform */
#include "acpi/gpe.asl"
/* Define the Thermal zones and methods for the platform */
#include "acpi/thermal.asl"
/* Define the System Indicators for the platform */
#include "acpi/si.asl"
}
/* End of ASL file */

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src/mainboard/msi/ms7721/irq_tables.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/pirq_routing.h>
#include <console/console.h>
#include <cpu/amd/amdfam15.h>
#include <device/pci_def.h>
#include <stdint.h>
#include <string.h>
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
u8 slot, u8 rfu)
{
pirq_info->bus = bus;
pirq_info->devfn = devfn;
pirq_info->irq[0].link = link0;
pirq_info->irq[0].bitmap = bitmap0;
pirq_info->irq[1].link = link1;
pirq_info->irq[1].bitmap = bitmap1;
pirq_info->irq[2].link = link2;
pirq_info->irq[2].bitmap = bitmap2;
pirq_info->irq[3].link = link3;
pirq_info->irq[3].bitmap = bitmap3;
pirq_info->slot = slot;
pirq_info->rfu = rfu;
}
unsigned long write_pirq_routing_table(unsigned long addr)
{
struct irq_routing_table *pirq;
struct irq_info *pirq_info;
u32 slot_num;
u8 *v;
u8 sum = 0;
int i;
/* Align the table to be 16 byte aligned. */
addr += 15;
addr &= ~15;
/* This table must be between 0xf0000 & 0x100000 */
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
v = (u8 *) (addr);
pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION;
pirq->rtr_bus = 0;
pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
pirq->exclusive_irqs = 0;
pirq->rtr_vendor = 0x1002;
pirq->rtr_device = 0x4384;
pirq->miniport_data = 0;
memset(pirq->rfu, 0, sizeof(pirq->rfu));
pirq_info = (void *)(&pirq->checksum + 1);
slot_num = 0;
/* pci bridge */
write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
0);
pirq_info++;
slot_num++;
pirq->size = 32 + 16 * slot_num;
for (i = 0; i < pirq->size; i++)
sum += v[i];
sum = pirq->checksum - sum;
if (sum != pirq->checksum) {
pirq->checksum = sum;
}
printk(BIOS_INFO, "write_pirq_routing_table done.\n");
return (unsigned long)pirq_info;
}

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src/mainboard/msi/ms7721/mainboard.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <arch/acpi.h>
#include <arch/io.h>
#include <console/console.h>
#include <cpu/amd/agesa/s3_resume.h>
#include <cpu/x86/msr.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
/*************************************************
* enable the dedicated function in thatcher board.
*************************************************/
static void mainboard_enable(device_t dev)
{
msr_t msr;
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
msr = rdmsr(0xC0011020);
msr.lo &= ~(1 << 28);
wrmsr(0xC0011020, msr);
msr = rdmsr(0xC0011022);
msr.lo &= ~(1 << 4);
msr.lo &= ~(1 << 13);
wrmsr(0xC0011022, msr);
msr = rdmsr(0xC0011023);
msr.lo &= ~(1 << 23);
wrmsr(0xC0011023, msr);
if (acpi_is_wakeup_s3())
agesawrapper_fchs3earlyrestore();
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};

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src/mainboard/msi/ms7721/mptable.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/cpu.h>
#include <arch/io.h>
#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include <cpu/amd/amdfam15.h>
#include <cpu/x86/lapic.h>
#include <device/pci.h>
#include <stdint.h>
#include <string.h>
#include "southbridge/amd/agesa/hudson/hudson.h"
u8 picr_data[] = {
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x1F,0x1F,0x1F,0x1F
};
u8 intr_data[0x54] = {
0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x10,0x11,0x12,0x13
};
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
{
mc->mpc_length += length;
mc->mpc_entry_count++;
}
static void my_smp_write_bus(struct mp_config_table *mc,
unsigned char id, const char *bustype)
{
struct mpc_config_bus *mpc;
mpc = smp_next_mpc_entry(mc);
memset(mpc, '\0', sizeof(*mpc));
mpc->mpc_type = MP_BUS;
mpc->mpc_busid = id;
memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
smp_add_mpc_entry(mc, sizeof(*mpc));
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
u8 byte;
/*
* By the time this function gets called, the IOAPIC registers
* have been written so they can be read to get the correct
* APIC ID and Version
*/
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
memcpy(mc->mpc_oem, "AMD ", 8);
smp_write_processors(mc);
//mptable_write_buses(mc, NULL, &bus_isa);
my_smp_write_bus(mc, 0, "PCI ");
my_smp_write_bus(mc, 1, "PCI ");
bus_isa = 0x02;
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00);
outb(picr_data[byte], 0xC01);
}
/* APIC IRQ routine */
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
}
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
/* IOMMU */
PCI_INT(0x0, 0x0, 0x0, 0x10);
PCI_INT(0x0, 0x0, 0x1, 0x11);
PCI_INT(0x0, 0x0, 0x2, 0x12);
PCI_INT(0x0, 0x0, 0x3, 0x13);
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
/* on board NIC & Slot PCIE. */
/* PCI slots */
device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
if (dev && dev->enabled) {
u8 bus_pci = dev->link_list->secondary;
/* PCI_SLOT 0. */
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
}
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
/* FCH PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
/* FCH PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, 0x11);
/* FCH PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, 0x12);
/* FCH PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, 0x13);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr, 0);
return (unsigned long)smp_write_config_table(v);
}

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src/mainboard/msi/ms7721/romstage.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <northbridge/amd/agesa/agesawrapper.h>
#include <arch/acpi.h>
#include <arch/cpu.h>
#include <arch/io.h>
#include <arch/stages.h>
#include <cbmem.h>
#include <console/console.h>
#include <cpu/amd/agesa/s3_resume.h>
#include <cpu/amd/car.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/pnp_def.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
#include <southbridge/amd/agesa/hudson/smbus.h>
#include <stdint.h>
#include <string.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8728f/it8728f.h>
#define MMIO_NON_POSTED_START 0xfed00000
#define MMIO_NON_POSTED_END 0xfedfffff
#define SB_MMIO 0xFED80000
#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x))
#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO)
static void sbxxx_enable_48mhzout(void)
{
/* most likely programming to 48MHz out signal */
u32 reg32;
reg32 = SB_MMIO_MISC32(0x28);
reg32 &= 0xffc7ffff;
reg32 |= 0x00100000;
SB_MMIO_MISC32(0x28) = reg32;
reg32 = SB_MMIO_MISC32(0x40);
reg32 &= ~0x80u;
SB_MMIO_MISC32(0x40) = reg32;
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
u8 byte;
pci_devfn_t dev;
#if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)
hudson_pci_port80();
#endif
#if IS_ENABLED(CONFIG_POST_DEVICE_LPC)
hudson_lpc_port80();
#endif
amd_initmmio();
if (!cpu_init_detectedx && boot_cpu()) {
/* enable SIO LPC decode */
dev = PCI_DEV(0, 0x14, 3);
byte = pci_read_config8(dev, 0x48);
byte |= 3; /* 2e, 2f */
pci_write_config8(dev, 0x48, byte);
/* enable serial decode */
byte = pci_read_config8(dev, 0x44);
byte |= (1 << 6); /* 0x3f8 */
pci_write_config8(dev, 0x44, byte);
post_code(0x30);
/* enable SB MMIO space */
outb(0x24, 0xcd6);
outb(0x1, 0xcd7);
/* enable SIO clock */
sbxxx_enable_48mhzout();
ite_kill_watchdog(GPIO_DEV);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
ite_enable_3vsbsw(GPIO_DEV);
console_init();
/* turn on secondary smbus at b20 */
outb(0x28, 0xcd6);
byte = inb(0xcd7);
byte |= 1;
outb(byte, 0xcd7);
}
/* Halt if there was a built in self test failure */
post_code(0x34);
report_bist_failure(bist);
/* Load MPB */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37);
agesawrapper_amdinitreset();
post_code(0x39);
agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
post_code(0x40);
agesawrapper_amdinitpost();
post_code(0x41);
agesawrapper_amdinitenv();
disable_cache_as_ram();
} else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n");
post_code(0x60);
agesawrapper_amdinitresume();
amd_initcpuio();
agesawrapper_amds3laterestore();
post_code(0x61);
prepare_for_resume();
}
post_code(0x50);
copy_and_run();
post_code(0x54); /* Should never see this post code. */
}