mb/google/brya: Add Kconfig for SLP_S0_GATE
Nissa doesn't have a SLP_S0_GATE signal, so we shouldn't generate the related ACPI code. Therefore, move this behind a Kconfig which is currently selected by the brya and brask baseboards. BUG=b:197479026 TEST=Build brya0, check that there's no change to the generated dsdt.asl Change-Id: I5a73c6794f6d3977cbff47aeff571154e41944cc Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@ -39,6 +39,7 @@ config BOARD_GOOGLE_BRYA_COMMON
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config BOARD_GOOGLE_BASEBOARD_BRYA
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config BOARD_GOOGLE_BASEBOARD_BRYA
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def_bool n
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def_bool n
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select BOARD_GOOGLE_BRYA_COMMON
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select BOARD_GOOGLE_BRYA_COMMON
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select HAVE_SLP_S0_GATE
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select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_BANSHEE
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select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_BANSHEE
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select SOC_INTEL_ALDERLAKE_PCH_P
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select SOC_INTEL_ALDERLAKE_PCH_P
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select SYSTEM_TYPE_LAPTOP
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select SYSTEM_TYPE_LAPTOP
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@ -47,6 +48,7 @@ config BOARD_GOOGLE_BASEBOARD_BRASK
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def_bool n
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def_bool n
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select BOARD_GOOGLE_BRYA_COMMON
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select BOARD_GOOGLE_BRYA_COMMON
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select ENABLE_TCSS_DISPLAY_DETECTION if RUN_FSP_GOP
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select ENABLE_TCSS_DISPLAY_DETECTION if RUN_FSP_GOP
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select HAVE_SLP_S0_GATE
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select MEMORY_SODIMM
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select MEMORY_SODIMM
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select RT8168_GEN_ACPI_POWER_RESOURCE
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select RT8168_GEN_ACPI_POWER_RESOURCE
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select RT8168_GET_MAC_FROM_VPD
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select RT8168_GET_MAC_FROM_VPD
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@ -227,4 +229,7 @@ config MEMORY_SOLDERDOWN
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select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS
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select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS
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select HAVE_SPD_IN_CBFS
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select HAVE_SPD_IN_CBFS
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config HAVE_SLP_S0_GATE
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def_bool n
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endif # BOARD_GOOGLE_BRYA_COMMON
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endif # BOARD_GOOGLE_BRYA_COMMON
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@ -2,6 +2,7 @@
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#include <baseboard/gpio.h>
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#include <baseboard/gpio.h>
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#if CONFIG(HAVE_SLP_S0_GATE)
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/*
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/*
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* S0ix Entry/Exit Notifications
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* S0ix Entry/Exit Notifications
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* Called from \_SB.PEPD._DSM
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* Called from \_SB.PEPD._DSM
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@ -22,3 +23,4 @@ Method (MS0X, 1, Serialized)
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\_SB.PCI0.STXS(GPIO_SLP_S0_GATE);
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\_SB.PCI0.STXS(GPIO_SLP_S0_GATE);
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}
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}
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}
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}
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#endif
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