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soc/intel/skylake: align chromium Chrome OS config 

The chromium tree is currently using a different config for
Chrome OS than what is being built in coreboot.org. Align those
settings to reflect how skylake Chrome OS boards are actually
shipped to provide proper parity between coreboot.org and chromium.

Change-Id: I7ab9c1dfa8c6be03ac2125fb06cb7022f3befa97
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16313
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Aaron Durbin 2016-08-24 08:49:29 -05:00 committed by Furquan Shaikh
parent dde073829f
commit a6914d2343
2 changed files with 3 additions and 0 deletions
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2
src/soc/intel/skylake/Kconfig
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@ -56,9 +56,11 @@ config CPU_SPECIFIC_OPTIONS
config CHROMEOS config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC select CHROMEOS_RAMOOPS_DYNAMIC
select EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC select EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC
select SEPARATE_VERSTAGE
select VBOOT_EC_SLOW_UPDATE select VBOOT_EC_SLOW_UPDATE
select VBOOT_OPROM_MATTERS select VBOOT_OPROM_MATTERS
select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
select VBOOT_STARTS_IN_BOOTBLOCK
select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS
select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
select VIRTUAL_DEV_SWITCH select VIRTUAL_DEV_SWITCH

1
src/soc/intel/skylake/Makefile.inc
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@ -28,6 +28,7 @@ bootblock-y += pmutil.c
bootblock-y += tsc_freq.c bootblock-y += tsc_freq.c
verstage-y += flash_controller.c verstage-y += flash_controller.c
verstage-y += monotonic_timer.c
verstage-y += pch.c verstage-y += pch.c
verstage-$(CONFIG_UART_DEBUG) += uart_debug.c verstage-$(CONFIG_UART_DEBUG) += uart_debug.c