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C and other Super I/O cosmetic fixes. 

- Random coding style, whitespace and cosmetic fixes.
 
 - Consistently use the same spacing and 4-hexdigit port number format
   in the pnp_dev_info[] arrays.
 
 - Drop dead/unused code and less useful comments.
 
 - Add missing "(C)" characters and copyright years.
 
 - Shorten and simplify some code snippets.
 
 - Use u8/u16/etc. everywhere.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6073 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2010-11-15 19:35:14 +00:00
parent 2e9323e5be
commit a69d978be8
82 changed files with 656 additions and 861 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/superio/fintek/f71805f/superio.c
View File

@ -90,12 +90,12 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
/* TODO: Some of the 0x7f8 etc. values may not be correct. */
/* TODO: Some of the 0x07f8 etc. values may not be correct. */
{ &ops, F71805F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, F71805F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, F71805F_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, F71805F_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F71805F_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F71805F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, F71805F_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0}, },
{ &ops, F71805F_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, F71805F_GPIO, PNP_IRQ0, },
{ &ops, F71805F_PME, },
};

5
src/superio/fintek/f71859/superio.c
View File

@ -87,9 +87,8 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
/* TODO: Some of the 0x7f8 etc. values may not be correct. */
{ &ops, F71859_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
/* TODO: Some of the 0x07f8 etc. values may not be correct. */
{ &ops, F71859_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
};
static void enable_dev(device_t dev)

12
src/superio/fintek/f71863fg/superio.c
View File

@ -94,14 +94,14 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
/* TODO: Some of the 0x7f8 etc. values may not be correct. */
/* TODO: Some of the 0x07f8 etc. values may not be correct. */
{ &ops, F71863FG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, F71863FG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, F71863FG_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, F71863FG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F71863FG_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F71863FG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, F71863FG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
{ &ops, F71863FG_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, },
{ &ops, F71863FG_GPIO, },
{ &ops, F71863FG_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, F71863FG_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, },
{ &ops, F71863FG_GPIO, }
{ &ops, F71863FG_VID, PNP_IO0, {0x07f8, 0}, },
{ &ops, F71863FG_SPI, },
{ &ops, F71863FG_PME, },

8
src/superio/fintek/f71872/superio.c
View File

@ -92,12 +92,12 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
/* TODO: Some of the 0x7f8 etc. values may not be correct. */
/* TODO: Some of the 0x07f8 etc. values may not be correct. */
{ &ops, F71872_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, F71872_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, F71872_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, F71872_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F71872_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F71872_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, F71872_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
{ &ops, F71872_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, F71872_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, },
{ &ops, F71872_GPIO, PNP_IRQ0, },
{ &ops, F71872_VID, PNP_IO0, {0x0ff8, 0}, },

10
src/superio/fintek/f71889/superio.c
View File

@ -93,13 +93,13 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
/* TODO: Some of the 0x7f8 etc. values may not be correct. */
/* TODO: Some of the 0x07f8 etc. values may not be correct. */
{ &ops, F71889_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, F71889_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, F71889_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, F71889_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F71889_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F71889_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, F71889_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
{ &ops, F71889_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, },
{ &ops, F71889_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, F71889_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, },
{ &ops, F71889_GPIO, },
{ &ops, F71889_VID, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F71889_SPI, },

4
src/superio/intel/i3100/superio.c
View File

@ -91,8 +91,8 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, I3100_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, I3100_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, I3100_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, I3100_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
};
static void enable_dev(struct device *dev)

4
src/superio/ite/it8661f/superio.c
View File

@ -63,8 +63,8 @@ static struct device_operations ops = {
/* TODO: FDC, PP, IR, GPIO. */
static struct pnp_info pnp_dev_info[] = {
{ &ops, IT8661F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, IT8661F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
{ &ops, IT8661F_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, IT8661F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, },
};
static void enable_dev(struct device *dev)

6
src/superio/ite/it8671f/superio.c
View File

@ -65,9 +65,9 @@ static struct device_operations ops = {
/* TODO: FDC, PP, KBCM. */
static struct pnp_info pnp_dev_info[] = {
{ &ops, IT8671F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, IT8671F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
{ &ops, IT8671F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
{ &ops, IT8671F_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, IT8671F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, },
{ &ops, IT8671F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, },
};
static void enable_dev(struct device *dev)

6
src/superio/ite/it8673f/superio.c
View File

@ -67,9 +67,9 @@ static struct device_operations ops = {
/* TODO: FDC, PP, FAN, KBCM. */
static struct pnp_info pnp_dev_info[] = {
{ &ops, IT8673F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, IT8673F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
{ &ops, IT8673F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
{ &ops, IT8673F_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, IT8673F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, },
{ &ops, IT8673F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, },
};
static void enable_dev(struct device *dev)

4
src/superio/ite/it8705f/superio.c
View File

@ -69,8 +69,8 @@ static struct device_operations ops = {
/* TODO: FDC, PP, EC, GPIO, GAME, IR, MIDI. */
static struct pnp_info pnp_dev_info[] = {
{ &ops, IT8705F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, IT8705F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
{ &ops, IT8705F_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, IT8705F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, },
};
static void enable_dev(struct device *dev)

20
src/superio/ite/it8712f/superio.c
View File

@ -112,17 +112,17 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{&ops, IT8712F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xff8, 0},},
{&ops, IT8712F_SP1, PNP_IO0 | PNP_IRQ0, {0xff8, 0},},
{&ops, IT8712F_SP2, PNP_IO0 | PNP_IRQ0, {0xff8, 0},},
{&ops, IT8712F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xffc, 0},},
{&ops, IT8712F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xff8, 0}, {0xff8, 4},},
{&ops, IT8712F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xfff, 0}, {0xfff, 4},},
{ &ops, IT8712F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ff8, 0}, },
{ &ops, IT8712F_SP1, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, IT8712F_SP2, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, IT8712F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ffc, 0}, },
{ &ops, IT8712F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x0ff8, 0}, {0x0ff8, 4}, },
{ &ops, IT8712F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x0fff, 0}, {0x0fff, 4}, },
{ &ops, IT8712F_KBCM, PNP_IRQ0, },
{&ops, IT8712F_GPIO, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0, {0xfff, 0}, {0xff8, 0}, {0xff8, 0},},
{&ops, IT8712F_MIDI, PNP_IO0 | PNP_IRQ0, {0xff8, 0},},
{&ops, IT8712F_GAME, PNP_IO0, {0xfff, 0},},
{&ops, IT8712F_IR, PNP_IO0 | PNP_IRQ0, {0xff8, 0},},
{ &ops, IT8712F_GPIO, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0, {0x0fff, 0}, {0x0ff8, 0}, {0x0ff8, 0}, },
{ &ops, IT8712F_MIDI, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, IT8712F_GAME, PNP_IO0, {0x0fff, 0}, },
{ &ops, IT8712F_IR, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
};
static void enable_dev(struct device *dev)

16
src/superio/ite/it8716f/superio.c
View File

@ -136,17 +136,15 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
{ &ops, IT8716F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{&ops, IT8716F_SP1, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},},
{&ops, IT8716F_SP2, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},},
{ &ops, IT8716F_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, IT8716F_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, IT8716F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{&ops, IT8716F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0},
{0x7f8, 0x4},},
{&ops, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7ff, 0},
{0x7ff, 0x4},},
{ &ops, IT8716F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, },
{ &ops, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07ff, 0}, {0x07ff, 4}, },
{ &ops, IT8716F_KBCM, PNP_IRQ0, },
{&ops, IT8716F_GPIO, PNP_IO1 | PNP_IO2, {0, 0}, {0x7f8, 0}, {0x7f8, 0},},
{&ops, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, {0x7fe, 0x4},},
{&ops, IT8716F_GAME, PNP_IO0, {0x7ff, 0},},
{ &ops, IT8716F_GPIO, PNP_IO1 | PNP_IO2, {0, 0}, {0x07f8, 0}, {0x07f8, 0}, },
{ &ops, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, {0x07fe, 4}, },
{ &ops, IT8716F_GAME, PNP_IO0, {0x07ff, 0}, },
{ &ops, IT8716F_IR, },
};

6
src/superio/ite/it8718f/superio.c
View File

@ -69,9 +69,9 @@ static struct device_operations ops = {
/* TODO: FDC, PP, EC, KBCM, IR. */
static struct pnp_info pnp_dev_info[] = {
{ &ops, IT8718F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, IT8718F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
{ &ops, IT8718F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
{ &ops, IT8718F_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, IT8718F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, },
{ &ops, IT8718F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, },
};
static void enable_dev(struct device *dev)

2
src/superio/nsc/pc8374/Makefile.inc
View File

@ -19,5 +19,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
#config chip.h
ramstage-$(CONFIG_SUPERIO_NSC_PC8374) += superio.c

9
src/superio/nsc/pc8374/pc8374_early_init.c
View File

@ -22,18 +22,19 @@
#include <arch/romcc_io.h>
#include "pc8374.h"
/* things that Must Be Done to get this chip working */
/* Straight from the data book */
static void pc8374_enable(unsigned iobase, u8 *init)
static void pc8374_enable(u16 iobase, u8 *init)
{
u8 val, count;
outb(0x29, iobase);
val = inb(iobase + 1);
val |= 0x91;
outb(val, iobase + 1);
for (count = 0; count < 255; count++)
if (inb(iobase + 1) == 0x91)
break;
for (; *init; init++) {
outb(*init, iobase);
val = inb(iobase + 1);
@ -45,7 +46,7 @@ static void pc8374_enable(unsigned iobase, u8 *init)
}
}
static void pc8374_enable_dev(device_t dev, unsigned iobase)
static void pc8374_enable_dev(device_t dev, u16 iobase)
{
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);

24
src/superio/nsc/pc8374/superio.c
View File

@ -33,15 +33,12 @@
static void init(device_t dev)
{
struct superio_nsc_pc8374_config *conf;
struct superio_nsc_pc8374_config *conf = dev­>chip_info;
struct resource *res0;
/* Wishlist handle well known programming interfaces more
* generically.
*/
if (!dev->enabled) {
if (!dev->enabled)
return;
}
conf = dev->chip_info;
switch(dev->path.pnp.device) {
case PC8374_SP1:
res0 = find_resource(dev, PNP_IDX_IO0);
@ -68,18 +65,17 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
{ &ops, PC8374_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07fa, 0}, },
{ &ops, PC8374_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0}, },
{ &ops, PC8374_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
{ &ops, PC8374_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, PC8374_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, },
{ &ops, PC8374_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, PC8374_SWC, PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, },
{ &ops, PC8374_KBCM, PNP_IRQ0 },
{ &ops, PC8374_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
{ &ops, PC8374_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } },
{ &ops, PC8374_KBCM, PNP_IRQ0, },
{ &ops, PC8374_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, },
{ &ops, PC8374_GPIO, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, },
};
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &ops,
ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_nsc_pc8374_ops = {

2
src/superio/nsc/pc87309/Makefile.inc
View File

@ -18,5 +18,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
#config chip.h
ramstage-$(CONFIG_SUPERIO_NSC_PC87309) += superio.c

2
src/superio/nsc/pc87309/pc87309_early_serial.c
View File

@ -21,7 +21,7 @@
#include <arch/romcc_io.h>
#include "pc87309.h"
static void pc87309_enable_serial(device_t dev, unsigned int iobase)
static void pc87309_enable_serial(device_t dev, u16 iobase)
{
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);

15
src/superio/nsc/pc87309/superio.c
View File

@ -29,13 +29,12 @@
static void init(device_t dev)
{
struct superio_nsc_pc87309_config *conf;
struct superio_nsc_pc87309_config *conf = dev->chip_info;
struct resource *res0;
if (!dev->enabled) {
if (!dev->enabled)
return;
}
conf = dev->chip_info;
switch (dev->path.pnp.device) {
case PC87309_SP1:
res0 = find_resource(dev, PNP_IDX_IO0);
@ -62,11 +61,11 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
{ &ops, PC87309_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07fa, 0}, },
{ &ops, PC87309_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0}, },
{&ops, PC87309_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x7f8, 0},},
{&ops, PC87309_SP1, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},},
{ &ops, PC87309_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, },
{ &ops, PC87309_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
/* TODO: PM. */
{&ops, PC87309_KBCM, PNP_IRQ0},
{&ops, PC87309_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0}, {0x7f8, 0x4},},
{ &ops, PC87309_KBCM, PNP_IRQ0, },
{ &ops, PC87309_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x7f8, 4}, },
};
static void enable_dev(struct device *dev)

2
src/superio/nsc/pc87351/Makefile.inc
View File

@ -19,5 +19,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
#config chip.h
ramstage-$(CONFIG_SUPERIO_NSC_PC87351) += superio.c

2
src/superio/nsc/pc87351/pc87351_early_serial.c
View File

@ -22,7 +22,7 @@
#include <arch/romcc_io.h>
#include "pc87351.h"
static void pc87351_enable_serial(device_t dev, unsigned iobase)
static void pc87351_enable_serial(device_t dev, u16 iobase)
{
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);

29
src/superio/nsc/pc87351/superio.c
View File

@ -19,12 +19,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*
* Richard A Smith
* I derived this code from the pc87360 device and removed the stuff the 87351
* dosen't do.
*/
#include <arch/io.h>
#include <device/device.h>
#include <device/pnp.h>
@ -39,15 +33,12 @@
static void init(device_t dev)
{
struct superio_nsc_pc87351_config *conf;
struct superio_nsc_pc87351_config *conf = dev->chip_info;
struct resource *res0;
/* Wishlist handle well known programming interfaces more
* generically.
*/
if (!dev->enabled) {
if (!dev->enabled)
return;
}
conf = dev->chip_info;
switch(dev->path.pnp.device) {
case PC87351_SP1:
res0 = find_resource(dev, PNP_IDX_IO0);
@ -74,13 +65,13 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
{ &ops, PC87351_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07fa, 0}, },
{ &ops, PC87351_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0}, },
{ &ops, PC87351_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
{ &ops, PC87351_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, PC87351_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, },
{ &ops, PC87351_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, PC87351_SWC, PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, },
{ &ops, PC87351_KBCM, PNP_IRQ0 },
{ &ops, PC87351_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
{ &ops, PC87351_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } },
{ &ops, PC87351_FSD, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } },
{ &ops, PC87351_KBCM, PNP_IRQ0, },
{ &ops, PC87351_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, },
{ &ops, PC87351_GPIO, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, },
{ &ops, PC87351_FSD, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, },
};
static void enable_dev(struct device *dev)

2
src/superio/nsc/pc87360/Makefile.inc
View File

@ -19,5 +19,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
#config chip.h
ramstage-$(CONFIG_SUPERIO_NSC_PC87360) += superio.c

2
src/superio/nsc/pc87360/pc87360_early_serial.c
View File

@ -22,7 +22,7 @@
#include <arch/romcc_io.h>
#include "pc87360.h"
static void pc87360_enable_serial(device_t dev, unsigned iobase)
static void pc87360_enable_serial(device_t dev, u16 iobase)
{
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);

30
src/superio/nsc/pc87360/superio.c
View File

@ -33,15 +33,12 @@
static void init(device_t dev)
{
struct superio_nsc_pc87360_config *conf;
struct superio_nsc_pc87360_config *conf = dev->chip_info;
struct resource *res0;
/* Wishlist handle well known programming interfaces more
* generically.
*/
if (!dev->enabled) {
if (!dev->enabled)
return;
}
conf = dev->chip_info;
switch(dev->path.pnp.device) {
case PC87360_SP1:
res0 = find_resource(dev, PNP_IDX_IO0);
@ -68,21 +65,20 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
{ &ops, PC87360_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07fa, 0}, },
{ &ops, PC87360_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0}, },
{ &ops, PC87360_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
{ &ops, PC87360_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, PC87360_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, },
{ &ops, PC87360_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, PC87360_SWC, PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, },
{ &ops, PC87360_KBCM, PNP_IRQ0 },
{ &ops, PC87360_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
{ &ops, PC87360_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } },
{ &ops, PC87360_ACB, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } },
{ &ops, PC87360_FSCM, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } },
{ &ops, PC87360_WDT, PNP_IO0 | PNP_IRQ0, { 0xfffc, 0 } },
{ &ops, PC87360_KBCM, PNP_IRQ0, },
{ &ops, PC87360_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, },
{ &ops, PC87360_GPIO, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, },
{ &ops, PC87360_ACB, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, },
{ &ops, PC87360_FSCM, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, },
{ &ops, PC87360_WDT, PNP_IO0 | PNP_IRQ0, {0xfffc, 0}, },
};
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &ops,
ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_nsc_pc87360_ops = {

2
src/superio/nsc/pc87366/Makefile.inc
View File

@ -19,5 +19,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
#config chip.h
ramstage-$(CONFIG_SUPERIO_NSC_PC87366) += superio.c

2
src/superio/nsc/pc87366/pc87366_early_serial.c
View File

@ -22,7 +22,7 @@
#include <arch/romcc_io.h>
#include "pc87366.h"
static void pc87366_enable_serial(device_t dev, unsigned iobase)
static void pc87366_enable_serial(device_t dev, u16 iobase)
{
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);

27
src/superio/nsc/pc87366/superio.c
View File

@ -33,15 +33,12 @@
static void init(device_t dev)
{
struct superio_nsc_pc87366_config *conf;
struct superio_nsc_pc87366_config *conf = dev->chip_info;
struct resource *res0;
/* Wishlist handle well known programming interfaces more
* generically.
*/
if (!dev->enabled) {
if (!dev->enabled)
return;
}
conf = dev->chip_info;
switch(dev->path.pnp.device) {
case PC87366_SP1:
res0 = find_resource(dev, PNP_IDX_IO0);
@ -68,15 +65,15 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
{ &ops, PC87366_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07fa, 0}, },
{ &ops, PC87366_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0}, },
{ &ops, PC87366_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
{ &ops, PC87366_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, PC87366_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, },
{ &ops, PC87366_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, PC87366_SWC, PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, },
{ &ops, PC87366_KBCM, PNP_IRQ0 },
{ &ops, PC87366_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
{ &ops, PC87366_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } },
{ &ops, PC87366_ACB, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } },
{ &ops, PC87366_FSCM, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } },
{ &ops, PC87366_WDT, PNP_IO0 | PNP_IRQ0, { 0xfffc, 0 } },
{ &ops, PC87366_KBCM, PNP_IRQ0, },
{ &ops, PC87366_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, },
{ &ops, PC87366_GPIO, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, },
{ &ops, PC87366_ACB, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, },
{ &ops, PC87366_FSCM, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, },
{ &ops, PC87366_WDT, PNP_IO0 | PNP_IRQ0, {0xfffc, 0}, },
};
static void enable_dev(struct device *dev)

2
src/superio/nsc/pc87417/Makefile.inc
View File

@ -20,5 +20,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
#config chip.h
ramstage-$(CONFIG_SUPERIO_NSC_PC87417) += superio.c

4
src/superio/nsc/pc87417/pc87417.h
View File

@ -3,7 +3,7 @@
*
* Copyright (C) 2000 AG Electronics Ltd.
* Copyright (C) 2003-2004 Linux Networx
* Copyright (C) 2004 Tyan by yhlu
* Copyright (C) 2004 Tyan
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -115,7 +115,7 @@
#define PC87417_XWBCNF 0x16
#if defined(__PRE_RAM__) && !defined(__ROMCC__)
void pc87417_enable_serial(device_t dev, unsigned iobase);
void pc87417_enable_serial(device_t dev, u16 iobase);
void pc87417_enable_dev(device_t dev);
#endif

19
src/superio/nsc/pc87417/pc87417_early_init.c
View File

@ -3,7 +3,7 @@
*
* Copyright (C) 2000 AG Electronics Ltd.
* Copyright (C) 2003-2004 Linux Networx
* Copyright (C) 2004 Tyan by yhlu
* Copyright (C) 2004 Tyan
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -29,7 +29,7 @@ static void pc87417_disable_dev(device_t dev)
pnp_set_enable(dev, 0);
}
static void pc87417_enable_dev(device_t dev, unsigned iobase)
static void pc87417_enable_dev(device_t dev, u16 iobase)
{
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
@ -39,17 +39,16 @@ static void pc87417_enable_dev(device_t dev, unsigned iobase)
static void xbus_cfg(device_t dev)
{
uint8_t i, data;
uint16_t xbus_index;
u8 i, data;
u16 xbus_index;
pnp_set_logical_device(dev);
/* select proper BIOS size (4MB) */
pnp_write_config(dev, PC87417_XMEMCNF2, (pnp_read_config(dev, PC87417_XMEMCNF2)) | 0x04);
/* Select proper BIOS size (4MB). */
pnp_write_config(dev, PC87417_XMEMCNF2,
(pnp_read_config(dev, PC87417_XMEMCNF2)) | 0x04);
xbus_index = pnp_read_iobase(dev, 0x60);
/* enable writes to devices attached to XCS0 (XBUS Chip Select 0) */
for (i=0; i<= 0xf; i++) {
/* Enable writes to devices attached to XCS0 (XBUS Chip Select 0). */
for (i = 0; i <= 0xf; i++)
outb((i << 4), xbus_index + PC87417_HAP0);
}
return;
}

4
src/superio/nsc/pc87417/pc87417_early_serial.c
View File

@ -3,7 +3,7 @@
*
* Copyright (C) 2000 AG Electronics Ltd.
* Copyright (C) 2003-2004 Linux Networx
* Copyright (C) 2004 Tyan by yhlu
* Copyright (C) 2004 Tyan
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -23,7 +23,7 @@
#include <arch/romcc_io.h>
#include "pc87417.h"
void pc87417_enable_serial(device_t dev, unsigned iobase)
void pc87417_enable_serial(device_t dev, u16 iobase)
{
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);

27
src/superio/nsc/pc87417/superio.c
View File

@ -3,7 +3,7 @@
*
* Copyright (C) 2000 AG Electronics Ltd.
* Copyright (C) 2003-2004 Linux Networx
* Copyright (C) 2004 Tyan by yhlu
* Copyright (C) 2004 Tyan
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -34,15 +34,12 @@
static void init(device_t dev)
{
struct superio_nsc_pc87417_config *conf;
struct superio_nsc_pc87417_config *conf = dev->chip_info;
struct resource *res0;
/* Wishlist handle well known programming interfaces more
* generically.
*/
if (!dev->enabled) {
if (!dev->enabled)
return;
}
conf = dev->chip_info;
switch(dev->path.pnp.device) {
case PC87417_SP1:
res0 = find_resource(dev, PNP_IDX_IO0);
@ -69,14 +66,14 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
{ &ops, PC87417_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07fa, 0}, },
{ &ops, PC87417_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0}, },
{ &ops, PC87417_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
{ &ops, PC87417_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, PC87417_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, },
{ &ops, PC87417_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, PC87417_SWC, PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, },
{ &ops, PC87417_KBCM, PNP_IRQ0 },
{ &ops, PC87417_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
{ &ops, PC87417_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } },
{ &ops, PC87417_XBUS, PNP_IO0 | PNP_IRQ0, { 0xffe0, 0 } },
{ &ops, PC87417_RTC, PNP_IO0 | PNP_IO1, { 0xfffe, 0 }, {0xfffe, 0x4} },
{ &ops, PC87417_KBCM, PNP_IRQ0, },
{ &ops, PC87417_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, },
{ &ops, PC87417_GPIO, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, },
{ &ops, PC87417_XBUS, PNP_IO0 | PNP_IRQ0, {0xffe0, 0}, },
{ &ops, PC87417_RTC, PNP_IO0 | PNP_IO1, {0xfffe, 0}, {0xfffe, 4}, },
};
static void enable_dev(struct device *dev)

2
src/superio/nsc/pc87427/Makefile.inc
View File

@ -19,5 +19,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
#config chip.h
ramstage-$(CONFIG_SUPERIO_NSC_PC87427) += superio.c

20
src/superio/nsc/pc87427/pc87427_early_init.c
View File

@ -27,26 +27,28 @@ static void pc87427_disable_dev(device_t dev)
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
}
static void pc87427_enable_dev(device_t dev, unsigned iobase)
static void pc87427_enable_dev(device_t dev, u16 iobase)
{
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
}
static void xbus_cfg(device_t dev)
{
uint8_t i, data;
uint16_t xbus_index;
u8 i, data;
u16 xbus_index;
pnp_set_logical_device(dev);
/* select proper BIOS size (4MB) */
pnp_write_config(dev, PC87427_XMEMCNF2, (pnp_read_config(dev, PC87427_XMEMCNF2)) | 0x04);
/* Select proper BIOS size (4MB). */
pnp_write_config(dev, PC87427_XMEMCNF2,
(pnp_read_config(dev, PC87427_XMEMCNF2)) | 0x04);
xbus_index = pnp_read_iobase(dev, 0x60);
/* enable writes to devices attached to XCS0 (XBUS Chip Select 0) */
for (i=0; i<= 0xf; i++) {
/* Enable writes to devices attached to XCS0 (XBUS Chip Select 0). */
for (i = 0; i <= 0xf; i++)
outb((i << 4), xbus_index + PC87427_HAP0);
}
return;
}

37
src/superio/nsc/pc87427/superio.c
View File

@ -31,15 +31,12 @@
static void init(device_t dev)
{
struct superio_nsc_pc87427_config *conf;
struct superio_nsc_pc87427_config *conf = dev->chip_info;
struct resource *res0;
/* Wishlist handle well known programming interfaces more
* generically.
*/
if (!dev->enabled) {
if (!dev->enabled)
return;
}
conf = dev->chip_info;
switch(dev->path.pnp.device) {
case PC87427_SP1:
res0 = find_resource(dev, PNP_IDX_IO0);
@ -65,24 +62,22 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
{ &ops, PC87427_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07fa, 0}, },
{ &ops, PC87427_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, PC87427_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, PC87427_SWC, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0,
{ 0xfff0, 0 }, { 0xfffc, 0 }, { 0xfffc, 0 }, { 0xfff8, 0 } },
{ &ops, PC87427_KBCM, PNP_IRQ0 },
{ &ops, PC87427_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
{ &ops, PC87427_GPIO, PNP_IO0 | PNP_IRQ0, { 0xffe0, 0 } },
{ &ops, PC87427_WDT, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 } },
{ &ops, PC87427_FMC, PNP_IO0 | PNP_IRQ0, { 0xffe0, 0 } },
{ &ops, PC87427_XBUS, PNP_IO0 | PNP_IRQ0, { 0xffe0, 0 } },
{ &ops, PC87427_RTC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0xfffe, 0 }, { 0xfffe, 0 } },
{ &ops, PC87427_MHC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0xffe0, 0 }, { 0xffe0, 0 } },
{ &ops, PC87427_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, PC87427_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, PC87427_SWC, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0, {0xfff0, 0}, {0xfffc, 0}, {0xfffc, 0}, {0xfff8, 0}, },
{ &ops, PC87427_KBCM, PNP_IRQ0, },
{ &ops, PC87427_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, },
{ &ops, PC87427_GPIO, PNP_IO0 | PNP_IRQ0, {0xffe0, 0}, },
{ &ops, PC87427_WDT, PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, },
{ &ops, PC87427_FMC, PNP_IO0 | PNP_IRQ0, {0xffe0, 0}, },
{ &ops, PC87427_XBUS, PNP_IO0 | PNP_IRQ0, {0xffe0, 0}, },
{ &ops, PC87427_RTC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xfffe, 0}, {0xfffe, 0}, },
{ &ops, PC87427_MHC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xffe0, 0}, {0xffe0, 0}, },
};
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &ops,
ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_nsc_pc87427_ops = {

2
src/superio/nsc/pc97307/Makefile.inc
View File

@ -18,5 +18,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
#config chip.h
ramstage-$(CONFIG_SUPERIO_NSC_PC97307) += superio.c

41
src/superio/nsc/pc97307/superio.c
View File

@ -28,45 +28,37 @@
static void init(device_t dev)
{
struct superio_nsc_pc97307_config *conf;
struct superio_nsc_pc97307_config *conf = dev->chip_info;
struct resource *res0;
u8 reg8;
if (!dev->enabled) {
if (!dev->enabled)
return;
}
conf = dev->chip_info;
switch(dev->path.pnp.device) {
case PC97307_SP1:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com1);
break;
case PC97307_SP2:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com2);
break;
case PC97307_KBCK:
/* Enable keyboard */
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); /* Disable keyboard */
pnp_write_config(dev, 0xf0, 0x40); /* Set KBC clock to 8 Mhz */
pnp_set_enable(dev, 1); /* Enable keyboard */
pnp_write_config(dev, 0xf0, 0x40); /* Set KBC clock to 8 MHz. */
pnp_set_enable(dev, 1); /* Enable keyboard. */
pc_keyboard_init(&conf->keyboard);
break;
case PC97307_FDC:
{
unsigned reg;
/* Set up floppy in PS/2 mode */
/* Set up floppy in PS/2 mode. */
outb(0x09, SIO_CONFIG_RA);
reg = inb(SIO_CONFIG_RD);
reg = (reg & 0x3F) | 0x40;
outb(reg, SIO_CONFIG_RD);
outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */
reg8 = inb(SIO_CONFIG_RD);
reg8 = (reg8 & 0x3F) | 0x40;
outb(reg8, SIO_CONFIG_RD);
outb(reg8, SIO_CONFIG_RD); /* Have to write twice to change! */
break;
}
default:
break;
}
@ -81,21 +73,20 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, PC97307_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0xffb, 0 }, { 0xffb, 0x4}, },
{ &ops, PC97307_KBCM, PNP_IRQ0 },
{ &ops, PC97307_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x0ffb, 0}, {0x0ffb, 4}, },
{ &ops, PC97307_KBCM, PNP_IRQ0, },
{ &ops, PC97307_RTC, PNP_IO0 | PNP_IRQ0, {0xfffe, 0}, },
{ &ops, PC97307_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xfffa, 0}, },
{ &ops, PC97307_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x03fc, 0}, },
{ &ops, PC97307_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0xfff8, 0}, },
{ &ops, PC97307_SP1, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, },
{ &ops, PC97307_GPIO, PNP_IO0, { 0xfff8, 0 } },
{ &ops, PC97307_PM, PNP_IO0, { 0xfffe, 0 } },
{ &ops, PC97307_GPIO, PNP_IO0, {0xfff8, 0}, },
{ &ops, PC97307_PM, PNP_IO0, {0xfffe, 0}, },
};
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &ops,
ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_nsc_pc97307_ops = {

2
src/superio/nsc/pc97317/Makefile.inc
View File

@ -18,5 +18,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
#config chip.h
ramstage-$(CONFIG_SUPERIO_NSC_PC97317) += superio.c

16
src/superio/nsc/pc97317/pc97317_early_serial.c
View File

@ -24,28 +24,24 @@
#define PM_DEV PNP_DEV(0x2e, PC97317_PM)
#define PM_BASE 0xe8
/* The pc97317 needs clocks to be set up before the serial port will operate */
static void pc97317_enable_serial(device_t dev, unsigned iobase)
/* The PC97317 needs clocks to be set up before the serial port will operate. */
static void pc97317_enable_serial(device_t dev, u16 iobase)
{
/* Set base address of power management unit */
/* Set base address of power management unit. */
pnp_set_logical_device(PM_DEV);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, PM_BASE);
pnp_set_enable(dev, 1);
/* Use on-chip clock multiplier */
/* Use on-chip clock multiplier. */
outb(0x03, PM_BASE);
outb(inb(PM_BASE + 1) | 0x07, PM_BASE + 1);
/* Wait for the clock to stabilise */
/* Wait for the clock to stabilise. */
while(!(inb(PM_BASE + 1) & 0x80))
;
/* Set the base address of the port */
/* Set the base address of the port. */
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);

38
src/superio/nsc/pc97317/superio.c
View File

@ -28,47 +28,28 @@
static void init(device_t dev)
{
struct superio_nsc_pc97317_config *conf;
struct superio_nsc_pc97317_config *conf = dev->chip_info;
struct resource *res0;
if (!dev->enabled) {
if (!dev->enabled)
return;
}
conf = dev->chip_info;
switch(dev->path.pnp.device) {
case PC97317_SP1:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com1);
break;
case PC97317_SP2:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com2);
break;
case PC97317_KBCK:
/* Enable keyboard */
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); /* Disable keyboard */
pnp_write_config(dev, 0xf0, 0x40); /* Set KBC clock to 8 Mhz */
pnp_write_config(dev, 0xf0, 0x40); /* Set KBC clock to 8 MHz. */
pnp_set_enable(dev, 1); /* Enable keyboard */
pc_keyboard_init(&conf->keyboard);
break;
#if 0
case PC97317_FDC:
{
unsigned reg;
/* Set up floppy in PS/2 mode */
outb(0x09, SIO_CONFIG_RA);
reg = inb(SIO_CONFIG_RD);
reg = (reg & 0x3F) | 0x40;
outb(reg, SIO_CONFIG_RD);
outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */
break;
}
#endif
default:
break;
}
@ -83,21 +64,20 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, PC97317_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0xffb, 0 }, { 0xffb, 0x4}, },
{ &ops, PC97317_KBCM, PNP_IRQ0 },
{ &ops, PC97317_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x0ffb, 0}, {0x0ffb, 4}, },
{ &ops, PC97317_KBCM, PNP_IRQ0, },
{ &ops, PC97317_RTC, PNP_IO0 | PNP_IRQ0, {0xfffe, 0}, },
{ &ops, PC97317_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xfffa, 0}, },
{ &ops, PC97317_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x03fc, 0}, },
{ &ops, PC97317_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0xfff8, 0}, },
{ &ops, PC97317_SP1, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, },
{ &ops, PC97317_GPIO, PNP_IO0, { 0xfff8, 0 } },
{ &ops, PC97317_PM, PNP_IO0, { 0xfffe, 0 } },
{ &ops, PC97317_GPIO, PNP_IO0, {0xfff8, 0}, },
{ &ops, PC97317_PM, PNP_IO0, {0xfffe, 0}, },
};
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &ops,
ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations superio_nsc_pc97317_ops = {

2
src/superio/smsc/fdc37m60x/Makefile.inc
View File

@ -18,5 +18,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
#config chip.h
ramstage-$(CONFIG_SUPERIO_SMSC_FDC37M60X) += superio.c

6
src/superio/smsc/fdc37m60x/fdc37m60x_early_serial.c
View File

@ -24,7 +24,7 @@
/* The base address is 0x3f0 or 0x370, depending on the SYSOPT pin. */
#define SIO_BASE 0x3f0
#define SIO_INDEX SIO_BASE
#define SIO_DATA SIO_BASE+1
#define SIO_DATA (SIO_BASE + 1)
/* Global configuration registers. */
#define FDC37M60X_CONFIG_REG_CC 0x02 /* Configure Control. */
@ -37,7 +37,7 @@
/* The content of FDC37M60X_CONFIG_REG_LDN (index 0x07) must be set to the
LDN the register belongs to, before you can access the register. */
static void fdc37m60x_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
static void fdc37m60x_sio_write(uint8_t ldn, u8 index, u8 value)
{
outb(FDC37M60X_CONFIG_REG_LDN, SIO_BASE);
outb(ldn, SIO_DATA);
@ -46,7 +46,7 @@ static void fdc37m60x_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
}
/* Enable the peripheral devices on the FDC37M60X Super I/O chip. */
static void fdc37m60x_enable_serial(device_t dev, unsigned iobase)
static void fdc37m60x_enable_serial(device_t dev, u16 iobase)
{
/* (1) Enter the configuration state. */
outb(0x55, FDC37M60X_CONFIGURATION_PORT);

13
src/superio/smsc/fdc37m60x/superio.c
View File

@ -28,14 +28,11 @@
static void init(device_t dev)
{
struct superio_smsc_fdc37m60x_config *conf;
struct superio_smsc_fdc37m60x_config *conf = dev->chip_info;
struct resource *res0;
if (!dev->enabled) {
if (!dev->enabled)
return;
}
conf = dev->chip_info;
switch (dev->path.pnp.device) {
case FDC37M60X_FDC: /* TODO. */
@ -68,9 +65,9 @@ static struct device_operations ops = {
/* TODO: FDC, PP, AUX. */
static struct pnp_info pnp_dev_info[] = {
{ &ops, FDC37M60X_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, FDC37M60X_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
{ &ops, FDC37M60X_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
{ &ops, FDC37M60X_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, FDC37M60X_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, },
{ &ops, FDC37M60X_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, },
};
static void enable_dev(struct device *dev)

1
src/superio/smsc/fdc37n972/Makefile.inc
View File

@ -18,3 +18,4 @@
##
ramstage-$(CONFIG_SUPERIO_SMSC_FDC37N972) += fdc37n972.c

13
src/superio/smsc/fdc37n972/fdc37n972.c
View File

@ -27,13 +27,10 @@
static void init(device_t dev)
{
struct superio_smsc_fdc37n972_config *conf;
struct superio_smsc_fdc37n972_config *conf = dev->chip_info;
if (!dev->enabled) {
if (!dev->enabled)
return;
}
conf = dev->chip_info;
switch (dev->path.pnp.device) {
case FDC37N972_FDC: /* TODO. */
@ -56,9 +53,9 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, FDC37N972_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, FDC37N972_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, },
{ &ops, FDC37N972_KBDC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
{ &ops, FDC37N972_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, FDC37N972_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, },
{ &ops, FDC37N972_KBDC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, },
};
static void enable_dev(struct device *dev)

2
src/superio/smsc/lpc47b272/Makefile.inc
View File

@ -18,5 +18,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
#config chip.h
ramstage-$(CONFIG_SUPERIO_SMSC_LPC47B272) += superio.c

10
src/superio/smsc/lpc47b272/lpc47b272_early_serial.c
View File

@ -23,17 +23,15 @@
#include <arch/romcc_io.h>
#include "lpc47b272.h"
/** Enable access to the LPC47B272's configuration registers. */
static inline void pnp_enter_conf_state(device_t dev)
static void pnp_enter_conf_state(device_t dev)
{
unsigned port = dev>>8;
u16 port = dev >> 8;
outb(0x55, port);
}
/** Disable access to the LPC47B272's configuration registers. */
static void pnp_exit_conf_state(device_t dev)
{
unsigned port = dev>>8;
u16 port = dev >> 8;
outb(0xaa, port);
}
@ -44,7 +42,7 @@ static void pnp_exit_conf_state(device_t dev)
* @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
* @param iobase Processor I/O port address to assign to this serial device.
*/
static void lpc47b272_enable_serial(device_t dev, unsigned iobase)
static void lpc47b272_enable_serial(device_t dev, u16 iobase)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);

42
src/superio/smsc/lpc47b272/superio.c
View File

@ -63,10 +63,10 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
{ &ops, LPC47B272_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, LPC47B272_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, LPC47B272_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, LPC47B272_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, LPC47B272_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
{ &ops, LPC47B272_RT, PNP_IO0, { 0x780, 0 }, },
{ &ops, LPC47B272_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, LPC47B272_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, LPC47B272_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
{ &ops, LPC47B272_RT, PNP_IO0, {0x0780, 0}, },
};
/**
@ -105,13 +105,7 @@ static void lpc47b272_pnp_enable(device_t dev)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
if(dev->enabled) {
pnp_set_enable(dev, 1);
}
else {
pnp_set_enable(dev, 0);
}
pnp_set_enable(dev, (dev->enabled) ? 1 : 0);
pnp_exit_conf_state(dev);
}
@ -136,25 +130,21 @@ static void lpc47b272_init(device_t dev)
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com1);
break;
case LPC47B272_SP2:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com2);
break;
case LPC47B272_KBC:
pc_keyboard_init(&conf->keyboard);
break;
}
}
/** Enable access to the LPC47B272's configuration registers. */
static void pnp_enter_conf_state(device_t dev)
{
outb(0x55, dev->path.pnp.port);
}
/** Disable access to the LPC47B272's configuration registers. */
static void pnp_exit_conf_state(device_t dev)
{
outb(0xaa, dev->path.pnp.port);
@ -170,29 +160,31 @@ static void pnp_exit_conf_state(device_t dev)
*/
static void dump_pnp_device(device_t dev)
{
int register_index;
int i;
print_debug("\n");
for(register_index = 0; register_index <= LPC47B272_MAX_CONFIG_REGISTER; register_index++) {
uint8_t register_value;
for (i = 0; i <= LPC47B272_MAX_CONFIG_REGISTER; i++) {
u8 register_value;
if ((register_index & 0x0f) == 0) {
print_debug_hex8(register_index);
if ((i & 0x0f) == 0) {
print_debug_hex8(i);
print_debug_char(':');
}
/* Skip over 'register' that would cause exit from configuration mode */
if (register_index == 0xaa)
/*
* Skip over 'register' that would cause exit from
* configuration mode.
*/
if (i == 0xaa)
register_value = 0xaa;
else
register_value = pnp_read_config(dev, register_index);
register_value = pnp_read_config(dev, i);
print_debug_char(' ');
print_debug_hex8(register_value);
if ((register_index & 0x0f) == 0x0f) {
if ((i & 0x0f) == 0x0f)
print_debug("\n");
}
}
print_debug("\n");
}

2
src/superio/smsc/lpc47b397/Makefile.inc
View File

@ -20,5 +20,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
#config chip.h
ramstage-$(CONFIG_SUPERIO_SMSC_LPC47B397) += superio.c

10
src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c
View File

@ -20,28 +20,28 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
static void lpc47b397_gpio_offset_out(unsigned iobase, unsigned offset, unsigned value)
static void lpc47b397_gpio_offset_out(u16 iobase, u16 offset, u8 value)
{
outb(value, iobase + offset);
}
static unsigned lpc47b397_gpio_offset_in(unsigned iobase, unsigned offset)
static u8 lpc47b397_gpio_offset_in(u16 iobase, u16 offset)
{
return inb(iobase+offset);
}
#if 0
/* for GP60-GP64, GP66-GP85 */
/* For GP60-GP64, GP66-GP85. */
#define LPC47B397_GPIO_CNTL_INDEX 0x70
#define LPC47B397_GPIO_CNTL_DATA 0x71
static void lpc47b397_gpio_index_out(unsigned iobase, unsigned index, unsigned value)
static void lpc47b397_gpio_index_out(u16 iobase, u8 index, u8 value)
{
outb(index, iobase + LPC47B397_GPIO_CNTL_INDEX);
outb(value, iobase + LPC47B397_GPIO_CNTL_DATA);
}
static unsigned lpc47b397_gpio_index_in(unsigned iobase, unsigned index)
static u8 lpc47b397_gpio_index_in(u16 iobase, u8 index)
{
outb(index, iobase + LPC47B397_GPIO_CNTL_INDEX);
return inb(iobase + LPC47B397_GPIO_CNTL_DATA);

8
src/superio/smsc/lpc47b397/lpc47b397_early_serial.c
View File

@ -23,19 +23,19 @@
#include <arch/romcc_io.h>
#include "lpc47b397.h"
static inline void pnp_enter_conf_state(device_t dev)
static void pnp_enter_conf_state(device_t dev)
{
unsigned port = dev>>8;
u16 port = dev >> 8;
outb(0x55, port);
}
static void pnp_exit_conf_state(device_t dev)
{
unsigned port = dev>>8;
u16 port = dev >> 8;
outb(0xaa, port);
}
static void lpc47b397_enable_serial(device_t dev, unsigned iobase)
static void lpc47b397_enable_serial(device_t dev, u16 iobase)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);

80
src/superio/smsc/lpc47b397/superio.c
View File

@ -37,41 +37,42 @@ static void pnp_enter_conf_state(device_t dev)
{
outb(0x55, dev->path.pnp.port);
}
static void pnp_exit_conf_state(device_t dev)
{
outb(0xaa, dev->path.pnp.port);
}
static void pnp_write_index(unsigned long port_base, uint8_t reg, uint8_t value)
static void pnp_write_index(u16 port, u8 reg, u8 value)
{
outb(reg, port_base);
outb(value, port_base + 1);
outb(reg, port);
outb(value, port + 1);
}
static uint8_t pnp_read_index(unsigned long port_base, uint8_t reg)
static u8 pnp_read_index(u16 port, u8 reg)
{
outb(reg, port_base);
return inb(port_base + 1);
outb(reg, port);
return inb(port + 1);
}
static void enable_hwm_smbus(device_t dev)
{
/* enable SensorBus register access */
uint8_t reg, value;
reg = 0xf0;
value = pnp_read_config(dev, reg);
value |= 0x01;
pnp_write_config(dev, reg, value);
/* Enable SensorBus register access. */
u8 reg8;
reg8 = pnp_read_config(dev, 0xf0);
reg8 |= (1 << 1);
pnp_write_config(dev, 0xf0, reg8);
}
static void lpc47b397_init(device_t dev)
{
struct superio_smsc_lpc47b397_config *conf;
struct superio_smsc_lpc47b397_config *conf = dev->chip_info;
struct resource *res0;
if (!dev->enabled) {
if (!dev->enabled)
return;
}
conf = dev->chip_info;
switch(dev->path.pnp.device) {
case LPC47B397_SP1:
res0 = find_resource(dev, PNP_IDX_IO0);
@ -91,9 +92,7 @@ static void lpc47b397_pnp_set_resources(device_t dev)
{
pnp_enter_conf_state(dev);
pnp_set_resources(dev);
#if 0
dump_pnp_device(dev);
#endif
/* dump_pnp_device(dev); */
pnp_exit_conf_state(dev);
}
@ -104,14 +103,12 @@ static void lpc47b397_pnp_enable_resources(device_t dev)
switch(dev->path.pnp.device) {
case LPC47B397_HWM:
printk(BIOS_DEBUG, "lpc47b397 SensorBus Register Access enabled\n");
printk(BIOS_DEBUG, "LPC47B397 SensorBus register access enabled\n");
pnp_set_logical_device(dev);
enable_hwm_smbus(dev);
break;
}
#if 0
dump_pnp_device(dev);
#endif
/* dump_pnp_device(dev); */
pnp_exit_conf_state(dev);
}
@ -119,13 +116,7 @@ static void lpc47b397_pnp_enable(device_t dev)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
if(dev->enabled) {
pnp_set_enable(dev, 1);
}
else {
pnp_set_enable(dev, 0);
}
pnp_set_enable(dev, (dev->enabled) ? 1 : 0);
pnp_exit_conf_state(dev);
}
@ -145,9 +136,9 @@ static struct device_operations ops = {
#define SB_DATA2 0x0e
#define SB_DATA3 0x0f
static int lsmbus_read_byte(device_t dev, uint8_t address)
static int lsmbus_read_byte(device_t dev, u8 address)
{
unsigned device;
unsigned int device;
struct resource *res;
int result;
@ -155,24 +146,26 @@ static int lsmbus_read_byte(device_t dev, uint8_t address)
res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0);
pnp_write_index(res->base+HWM_INDEX, 0, device); /* why 0? */
pnp_write_index(res->base + HWM_INDEX, 0, device); /* Why 0? */
result = pnp_read_index(res->base+SB_INDEX, address); /* we only read it one byte one time */
/* We only read it one byte one time. */
result = pnp_read_index(res->base + SB_INDEX, address);
return result;
}
static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
{
unsigned device;
unsigned int device;
struct resource *res;
device = dev->path.i2c.device;
res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0);
pnp_write_index(res->base+HWM_INDEX, 0, device); /* why 0? */
pnp_write_index(res->base+HWM_INDEX, 0, device); /* Why 0? */
pnp_write_index(res->base+SB_INDEX, address, val); /* we only write it one byte one time */
/* We only write it one byte one time. */
pnp_write_index(res->base+SB_INDEX, address, val);
return 0;
}
@ -183,6 +176,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
.read_byte = lsmbus_read_byte,
.write_byte = lsmbus_write_byte,
};
static struct device_operations ops_hwm = {
.read_resources = pnp_read_resources,
.set_resources = lpc47b397_pnp_set_resources,
@ -196,11 +190,11 @@ static struct device_operations ops_hwm = {
static struct pnp_info pnp_dev_info[] = {
{ &ops, LPC47B397_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, LPC47B397_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, LPC47B397_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, LPC47B397_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, LPC47B397_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
{ &ops_hwm, LPC47B397_HWM, PNP_IO0, { 0x7f0, 0 }, },
{ &ops, LPC47B397_RT, PNP_IO0, { 0x780, 0 }, },
{ &ops, LPC47B397_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, LPC47B397_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, LPC47B397_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
{ &ops_hwm, LPC47B397_HWM, PNP_IO0, {0x07f0, 0}, },
{ &ops, LPC47B397_RT, PNP_IO0, {0x0780, 0}, },
};
static void enable_dev(struct device *dev)

2
src/superio/smsc/lpc47m10x/Makefile.inc
View File

@ -22,5 +22,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
#config chip.h
ramstage-$(CONFIG_SUPERIO_SMSC_LPC47M10X) += superio.c

2
src/superio/smsc/lpc47m10x/lpc47m10x.h
View File

@ -30,7 +30,7 @@
#define LPC47M10X2_KBC 7 /* Keyboard & Mouse */
#define LPC47M10X2_GAME 9 /* GAME */
#define LPC47M10X2_PME 10 /* PME reg*/
#define LPC47M10X2_MPU 10 /* MPE -- who knows -- reg*/
#define LPC47M10X2_MPU 10 /* MPE -- who knows -- reg*/ // FIXME
#define LPC47M10X2_MAX_CONFIG_REGISTER 0x5F

13
src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c
View File

@ -1,6 +1,5 @@
/*
* lpc47m10x_early_serial.c: Pre-RAM driver for SMSC LPC47M10X2 Super I/O chip
* derived from lpc47n217
* This file is part of the coreboot project.
*
* Copyright (C) 2005 Digital Design Corporation
*
@ -22,17 +21,15 @@
#include <arch/romcc_io.h>
#include "lpc47m10x.h"
/** Enable access to the LPC47M10X2's configuration registers. */
static inline void pnp_enter_conf_state(device_t dev)
static void pnp_enter_conf_state(device_t dev)
{
unsigned port = dev>>8;
u16 port = dev >> 8;
outb(0x55, port);
}
/** Disable access to the LPC47M10X2's configuration registers. */
static void pnp_exit_conf_state(device_t dev)
{
unsigned port = dev>>8;
u16 port = dev >> 8;
outb(0xaa, port);
}
@ -43,7 +40,7 @@ static void pnp_exit_conf_state(device_t dev)
* @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
* @param iobase Processor I/O port address to assign to this serial device.
*/
static void lpc47m10x_enable_serial(device_t dev, unsigned iobase)
static void lpc47m10x_enable_serial(device_t dev, u16 iobase)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);

50
src/superio/smsc/lpc47m10x/superio.c
View File

@ -1,11 +1,11 @@
/*
* superio.c: RAM driver for SMSC LPC47M10X2 Super I/O chip
* This file is part of the coreboot project.
*
* Copyright 2000 AG Electronics Ltd.
* Copyright 2003-2004 Linux Networx
* Copyright 2004 Tyan
* Copyright (C) 2000 AG Electronics Ltd.
* Copyright (C) 2003-2004 Linux Networx
* Copyright (C) 2004 Tyan
* Copyright (C) 2005 Digital Design Corporation
* Copyright (C) Ron Minnich, LANL
* Copyright (C) 2006 Ron Minnich, LANL
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -62,9 +62,9 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
{ &ops, LPC47M10X2_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, LPC47M10X2_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, LPC47M10X2_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, LPC47M10X2_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, LPC47M10X2_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
{ &ops, LPC47M10X2_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, LPC47M10X2_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, LPC47M10X2_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
};
/**
@ -103,13 +103,7 @@ static void lpc47m10x_pnp_enable(device_t dev)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
if(dev->enabled) {
pnp_set_enable(dev, 1);
}
else {
pnp_set_enable(dev, 0);
}
pnp_set_enable(dev, (dev->enabled) ? 1 : 0);
pnp_exit_conf_state(dev);
}
@ -134,25 +128,21 @@ static void lpc47m10x_init(device_t dev)
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com1);
break;
case LPC47M10X2_SP2:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com2);
break;
case LPC47M10X2_KBC:
pc_keyboard_init(&conf->keyboard);
break;
}
}
/** Enable access to the LPC47M10X2's configuration registers. */
static void pnp_enter_conf_state(device_t dev)
{
outb(0x55, dev->path.pnp.port);
}
/** Disable access to the LPC47M10X2's configuration registers. */
static void pnp_exit_conf_state(device_t dev)
{
outb(0xaa, dev->path.pnp.port);
@ -168,29 +158,31 @@ static void pnp_exit_conf_state(device_t dev)
*/
static void dump_pnp_device(device_t dev)
{
int register_index;
int i;
print_debug("\n");
for(register_index = 0; register_index <= LPC47M10X2_MAX_CONFIG_REGISTER; register_index++) {
uint8_t register_value;
for (i = 0; i <= LPC47M10X2_MAX_CONFIG_REGISTER; i++) {
u8 register_value;
if ((register_index & 0x0f) == 0) {
print_debug_hex8(register_index);
if ((i & 0x0f) == 0) {
print_debug_hex8(i);
print_debug_char(':');
}
/* Skip over 'register' that would cause exit from configuration mode */
if (register_index == 0xaa)
/*
* Skip over 'register' that would cause exit from
* configuration mode.
*/
if (i == 0xaa)
register_value = 0xaa;
else
register_value = pnp_read_config(dev, register_index);
register_value = pnp_read_config(dev, i);
print_debug_char(' ');
print_debug_hex8(register_value);
if ((register_index & 0x0f) == 0x0f) {
if ((i & 0x0f) == 0x0f)
print_debug("\n");
}
}
print_debug("\n");
}

2
src/superio/smsc/lpc47m15x/Makefile.inc
View File

@ -17,5 +17,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
#config chip.h
ramstage-$(CONFIG_SUPERIO_SMSC_LPC47M15X) += superio.c

8
src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c
View File

@ -22,19 +22,19 @@
#include <arch/romcc_io.h>
#include "lpc47m15x.h"
static inline void pnp_enter_conf_state(device_t dev)
static void pnp_enter_conf_state(device_t dev)
{
unsigned port = dev>>8;
u16 port = dev >> 8;
outb(0x55, port);
}
static void pnp_exit_conf_state(device_t dev)
{
unsigned port = dev>>8;
u16 port = dev >> 8;
outb(0xaa, port);
}
static inline void lpc47m15x_enable_serial(device_t dev, unsigned iobase)
static void lpc47m15x_enable_serial(device_t dev, u16 iobase)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);

19
src/superio/smsc/lpc47m15x/superio.c
View File

@ -58,14 +58,15 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
{ &ops, LPC47M15X_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, LPC47M15X_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, LPC47M15X_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, LPC47M15X_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, LPC47M15X_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
{ &ops, LPC47M15X_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, LPC47M15X_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, LPC47M15X_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
};
static void enable_dev(device_t dev)
{
pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
pnp_enable_devices(dev, &pnp_ops,
ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
static void lpc47m15x_pnp_set_resources(device_t dev)
@ -86,13 +87,7 @@ static void lpc47m15x_pnp_enable(device_t dev)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
if(dev->enabled) {
pnp_set_enable(dev, 1);
}
else {
pnp_set_enable(dev, 0);
}
pnp_set_enable(dev, (dev->enabled) ? 1 : 0);
pnp_exit_conf_state(dev);
}
@ -109,12 +104,10 @@ static void lpc47m15x_init(device_t dev)
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com1);
break;
case LPC47M15X_SP2:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com2);
break;
case LPC47M15X_KBC:
pc_keyboard_init(&conf->keyboard);
break;

2
src/superio/smsc/lpc47n217/Makefile.inc
View File

@ -18,5 +18,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
#config chip.h
ramstage-$(CONFIG_SUPERIO_SMSC_LPC47N217) += superio.c

31
src/superio/smsc/lpc47n217/lpc47n217_early_serial.c
View File

@ -24,17 +24,15 @@
#include <assert.h>
#include "lpc47n217.h"
/** Enable access to the LPC47N217's configuration registers. */
static inline void pnp_enter_conf_state(device_t dev)
static void pnp_enter_conf_state(device_t dev)
{
unsigned port = dev>>8;
u16 port = dev >> 8;
outb(0x55, port);
}
/** Disable access to the LPC47N217's configuration registers. */
static void pnp_exit_conf_state(device_t dev)
{
unsigned port = dev>>8;
u16 port = dev >> 8;
outb(0xaa, port);
}
@ -44,24 +42,21 @@ static void pnp_exit_conf_state(device_t dev)
* @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
* @param iobase Base I/O port for the logical device.
*/
void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)
void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase)
{
/* LPC47N217 requires base ports to be a multiple of 4 */
/* LPC47N217 requires base ports to be a multiple of 4. */
ASSERT(!(iobase & 0x3));
switch(dev & 0xFF) {
case LPC47N217_PP:
pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
break;
case LPC47N217_SP1:
pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
break;
case LPC47N217_SP2:
pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
break;
default:
break;
}
@ -81,37 +76,29 @@ void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)
*/
void lpc47n217_pnp_set_enable(device_t dev, int enable)
{
uint8_t power_register = 0;
uint8_t power_mask = 0;
uint8_t current_power;
uint8_t new_power;
u8 power_register = 0, power_mask = 0, current_power, new_power;
switch(dev & 0xFF) {
case LPC47N217_PP:
power_register = 0x01;
power_mask = 0x04;
break;
case LPC47N217_SP1:
power_register = 0x02;
power_mask = 0x08;
break;
case LPC47N217_SP2:
power_register = 0x02;
power_mask = 0x80;
break;
default:
return;
}
current_power = pnp_read_config(dev, power_register);
new_power = current_power & ~power_mask; /* disable by default */
new_power = current_power & ~power_mask; /* Disable by default. */
if (enable)
new_power |= power_mask; /* Enable */
new_power |= power_mask; /* Enable. */
pnp_write_config(dev, power_register, new_power);
}
@ -122,7 +109,7 @@ void lpc47n217_pnp_set_enable(device_t dev, int enable)
* @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
* @param iobase Processor I/O port address to assign to this serial device.
*/
static void lpc47n217_enable_serial(device_t dev, unsigned iobase)
static void lpc47n217_enable_serial(device_t dev, u16 iobase)
{
/*
* NOTE: Cannot use pnp_set_XXX() here because they assume chip

135
src/superio/smsc/lpc47n217/superio.c
View File

@ -22,7 +22,6 @@
*/
/* RAM-based driver for SMSC LPC47N217 Super I/O chip. */
/* Based on coreboot code for SMSC 47B397. */
#include <arch/io.h>
#include <device/device.h>
@ -43,13 +42,11 @@ static void lpc47n217_pnp_set_resources(device_t dev);
static void lpc47n217_pnp_enable_resources(device_t dev);
static void lpc47n217_pnp_enable(device_t dev);
static void lpc47n217_init(device_t dev);
static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource);
static void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase);
static void lpc47n217_pnp_set_drq(device_t dev, unsigned drq);
static void lpc47n217_pnp_set_irq(device_t dev, unsigned irq);
static void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase);
static void lpc47n217_pnp_set_drq(device_t dev, u8 drq);
static void lpc47n217_pnp_set_irq(device_t dev, u8 irq);
static void lpc47n217_pnp_set_enable(device_t dev, int enable);
static void pnp_enter_conf_state(device_t dev);
static void pnp_exit_conf_state(device_t dev);
@ -68,8 +65,8 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
{ &ops, LPC47N217_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, LPC47N217_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, LPC47N217_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }
{ &ops, LPC47N217_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, LPC47N217_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }
};
/**
@ -88,6 +85,9 @@ static void enable_dev(device_t dev)
* Configure the specified Super I/O device with the resources (I/O space,
* etc.) that have been allocate for it.
*
* NOTE: Cannot use pnp_set_resources() here because it assumes chip
* support for logical devices, which the LPC47N217 doesn't have.
*
* @param dev Pointer to structure describing a Super I/O device.
*/
static void lpc47n217_pnp_set_resources(device_t dev)
@ -95,46 +95,31 @@ static void lpc47n217_pnp_set_resources(device_t dev)
struct resource *res;
pnp_enter_conf_state(dev);
/* NOTE: Cannot use pnp_set_resources() here because it assumes chip
* support for logical devices, which the LPC47N217 doesn't have
*/
for (res = dev->resource_list; res; res = res->next)
lpc47n217_pnp_set_resource(dev, res);
/* dump_pnp_device(dev); */
pnp_exit_conf_state(dev);
}
static void lpc47n217_pnp_enable_resources(device_t dev)
{
pnp_enter_conf_state(dev);
/*
* NOTE: Cannot use pnp_enable_resources() here because it assumes chip
* support for logical devices, which the LPC47N217 doesn't have.
*/
lpc47n217_pnp_set_enable(dev, 1);
pnp_exit_conf_state(dev);
}
static void lpc47n217_pnp_enable(device_t dev)
static void lpc47n217_pnp_enable_resources(device_t dev)
{
pnp_enter_conf_state(dev);
lpc47n217_pnp_set_enable(dev, 1);
pnp_exit_conf_state(dev);
}
/*
* NOTE: Cannot use pnp_set_enable() here because it assumes chip
* support for logical devices, which the LPC47N217 doesn't have.
*/
if(dev->enabled) {
lpc47n217_pnp_set_enable(dev, 1);
}
else {
lpc47n217_pnp_set_enable(dev, 0);
}
static void lpc47n217_pnp_enable(device_t dev)
{
pnp_enter_conf_state(dev);
lpc47n217_pnp_set_enable(dev, (dev->enabled) ? 1 : 0);
pnp_exit_conf_state(dev);
}
@ -159,7 +144,6 @@ static void lpc47n217_init(device_t dev)
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com1);
break;
case LPC47N217_SP2:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com2);
@ -175,21 +159,19 @@ static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource)
return;
}
/* Now store the resource */
/* Now store the resource. */
/*
* NOTE: Cannot use pnp_set_XXX() here because they assume chip
* support for logical devices, which the LPC47N217 doesn't have.
*/
if (resource->flags & IORESOURCE_IO) {
lpc47n217_pnp_set_iobase(dev, resource->base);
}
else if (resource->flags & IORESOURCE_DRQ) {
} else if (resource->flags & IORESOURCE_DRQ) {
lpc47n217_pnp_set_drq(dev, resource->base);
}
else if (resource->flags & IORESOURCE_IRQ) {
} else if (resource->flags & IORESOURCE_IRQ) {
lpc47n217_pnp_set_irq(dev, resource->base);
}
else {
} else {
printk(BIOS_ERR, "ERROR: %s %02x unknown resource type\n",
dev_path(dev), resource->index);
return;
@ -199,7 +181,7 @@ static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource)
report_resource_stored(dev, resource, "");
}
static void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)
static void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase)
{
ASSERT(!(iobase & 0x3));
@ -207,30 +189,28 @@ static void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase)
case LPC47N217_PP:
pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
break;
case LPC47N217_SP1:
pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
break;
case LPC47N217_SP2:
pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
break;
default:
BUG();
break;
}
}
static void lpc47n217_pnp_set_drq(device_t dev, unsigned drq)
static void lpc47n217_pnp_set_drq(device_t dev, u8 drq)
{
if (dev->path.pnp.device == LPC47N217_PP) {
const uint8_t PP_DMA_MASK = 0x0F;
const uint8_t PP_DMA_SELECTION_REGISTER = 0x26;
uint8_t current_config = pnp_read_config(dev, PP_DMA_SELECTION_REGISTER);
uint8_t new_config;
const u8 PP_DMA_MASK = 0x0F;
const u8 PP_DMA_SELECTION_REGISTER = 0x26;
u8 current_config, new_config;
ASSERT(!(drq & ~PP_DMA_MASK)); /* DRQ out of range?? */
if (dev->path.pnp.device == LPC47N217_PP) {
current_config = pnp_read_config(dev,
PP_DMA_SELECTION_REGISTER);
ASSERT(!(drq & ~PP_DMA_MASK)); /* DRQ out of range? */
new_config = (current_config & ~PP_DMA_MASK) | drq;
pnp_write_config(dev, PP_DMA_SELECTION_REGISTER, new_config);
} else {
@ -238,36 +218,31 @@ static void lpc47n217_pnp_set_drq(device_t dev, unsigned drq)
}
}
static void lpc47n217_pnp_set_irq(device_t dev, unsigned irq)
static void lpc47n217_pnp_set_irq(device_t dev, u8 irq)
{
uint8_t irq_config_register = 0;
uint8_t irq_config_mask = 0;
uint8_t current_config;
uint8_t new_config;
u8 irq_config_register = 0, irq_config_mask = 0;
u8 current_config, new_config;
switch(dev->path.pnp.device) {
case LPC47N217_PP:
irq_config_register = 0x27;
irq_config_mask = 0x0F;
break;
case LPC47N217_SP1:
irq_config_register = 0x28;
irq_config_mask = 0xF0;
irq <<= 4;
break;
case LPC47N217_SP2:
irq_config_register = 0x28;
irq_config_mask = 0x0F;
break;
default:
BUG();
return;
}
ASSERT(!(irq & ~irq_config_mask)); /* IRQ out of range?? */
ASSERT(!(irq & ~irq_config_mask)); /* IRQ out of range? */
current_config = pnp_read_config(dev, irq_config_register);
new_config = (current_config & ~irq_config_mask) | irq;
@ -276,54 +251,44 @@ static void lpc47n217_pnp_set_irq(device_t dev, unsigned irq)
static void lpc47n217_pnp_set_enable(device_t dev, int enable)
{
uint8_t power_register = 0;
uint8_t power_mask = 0;
uint8_t current_power;
uint8_t new_power;
u8 power_register = 0, power_mask = 0, current_power, new_power;
switch(dev->path.pnp.device) {
case LPC47N217_PP:
power_register = 0x01;
power_mask = 0x04;
break;
case LPC47N217_SP1:
power_register = 0x02;
power_mask = 0x08;
break;
case LPC47N217_SP2:
power_register = 0x02;
power_mask = 0x80;
break;
default:
BUG();
return;
}
current_power = pnp_read_config(dev, power_register);
new_power = current_power & ~power_mask; /* disable by default */
new_power = current_power & ~power_mask; /* Disable by default. */
if (enable) {
struct resource* ioport_resource = find_resource(dev, PNP_IDX_IO0);
struct resource* ioport_resource;
ioport_resource = find_resource(dev, PNP_IDX_IO0);
lpc47n217_pnp_set_iobase(dev, ioport_resource->base);
new_power |= power_mask; /* Enable */
new_power |= power_mask; /* Enable. */
} else {
lpc47n217_pnp_set_iobase(dev, 0);
}
pnp_write_config(dev, power_register, new_power);
}
/** Enable access to the LPC47N217's configuration registers. */
static void pnp_enter_conf_state(device_t dev)
{
outb(0x55, dev->path.pnp.port);
}
/** Disable access to the LPC47N217's configuration registers. */
static void pnp_exit_conf_state(device_t dev)
{
outb(0xaa, dev->path.pnp.port);
@ -339,29 +304,31 @@ static void pnp_exit_conf_state(device_t dev)
*/
static void dump_pnp_device(device_t dev)
{
int register_index;
int i;
print_debug("\n");
for(register_index = 0; register_index <= LPC47N217_MAX_CONFIG_REGISTER; register_index++) {
uint8_t register_value;
for (i = 0; i <= LPC47N217_MAX_CONFIG_REGISTER; i++) {
u8 register_value;
if ((register_index & 0x0f) == 0) {
print_debug_hex8(register_index);
if ((i & 0x0f) == 0) {
print_debug_hex8(i);
print_debug_char(':');
}
/* Skip over 'register' that would cause exit from configuration mode */
if (register_index == 0xaa)
/*
* Skip over 'register' that would cause exit from
* configuration mode.
*/
if (i == 0xaa)
register_value = 0xaa;
else
register_value = pnp_read_config(dev, register_index);
register_value = pnp_read_config(dev, i);
print_debug_char(' ');
print_debug_hex8(register_value);
if ((register_index & 0x0f) == 0x0f) {
if ((i & 0x0f) == 0x0f)
print_debug("\n");
}
}
print_debug("\n");
}

1
src/superio/smsc/lpc47n227/Makefile.inc
View File

@ -18,3 +18,4 @@
##
ramstage-$(CONFIG_SUPERIO_SMSC_LPC47N227) += superio.c

39
src/superio/smsc/lpc47n227/lpc47n227_early_serial.c
View File

@ -23,25 +23,15 @@
#include <arch/romcc_io.h>
#include "lpc47n227.h"
/**
* Enable access to the LPC47N227's configuration registers.
*
* @param dev High 8 bits = Super I/O port.
*/
static inline void pnp_enter_conf_state(device_t dev)
static void pnp_enter_conf_state(device_t dev)
{
unsigned port = dev >> 8;
u16 port = dev >> 8;
outb(0x55, port);
}
/**
* Disable access to the LPC47N227's configuration registers.
*
* @param dev High 8 bits = Super I/O port.
*/
static void pnp_exit_conf_state(device_t dev)
{
unsigned port = dev >> 8;
u16 port = dev >> 8;
outb(0xaa, port);
}
@ -51,24 +41,21 @@ static void pnp_exit_conf_state(device_t dev)
* @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
* @param iobase Base I/O port for the logical device.
*/
void lpc47n227_pnp_set_iobase(device_t dev, unsigned iobase)
void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase)
{
// LPC47N227 requires base ports to be a multiple of 4
/* LPC47N227 requires base ports to be a multiple of 4. */
ASSERT(!(iobase & 0x3));
switch (dev & 0xFF) {
case LPC47N227_PP:
pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
break;
case LPC47N227_SP1:
pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
break;
case LPC47N227_SP2:
pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
break;
default:
break;
}
@ -88,37 +75,29 @@ void lpc47n227_pnp_set_iobase(device_t dev, unsigned iobase)
*/
void lpc47n227_pnp_set_enable(device_t dev, int enable)
{
uint8_t power_register = 0;
uint8_t power_mask = 0;
uint8_t current_power;
uint8_t new_power;
u8 power_register = 0, power_mask = 0, current_power, new_power;
switch (dev & 0xFF) {
case LPC47N227_PP:
power_register = 0x01;
power_mask = 0x04;
break;
case LPC47N227_SP1:
power_register = 0x02;
power_mask = 0x08;
break;
case LPC47N227_SP2:
power_register = 0x02;
power_mask = 0x80;
break;
default:
return;
}
current_power = pnp_read_config(dev, power_register);
new_power = current_power & ~power_mask; // disable by default
new_power = current_power & ~power_mask; /* Disable by default. */
if (enable)
new_power |= power_mask; // Enable
new_power |= power_mask; /* Enable. */
pnp_write_config(dev, power_register, new_power);
}
@ -129,7 +108,7 @@ void lpc47n227_pnp_set_enable(device_t dev, int enable)
* @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
* @param iobase Processor I/O port address to assign to this serial device.
*/
static void lpc47n227_enable_serial(device_t dev, unsigned iobase)
static void lpc47n227_enable_serial(device_t dev, u16 iobase)
{
/*
* NOTE: Cannot use pnp_set_XXX() here because they assume chip

108
src/superio/smsc/lpc47n227/superio.c
View File

@ -33,19 +33,17 @@
#include "chip.h"
#include "lpc47n227.h"
// Forward declarations
/* Forward declarations. */
static void enable_dev(device_t dev);
void lpc47n227_pnp_set_resources(device_t dev);
void lpc47n227_pnp_enable_resources(device_t dev);
void lpc47n227_pnp_enable(device_t dev);
static void lpc47n227_init(device_t dev);
static void lpc47n227_pnp_set_resource(device_t dev, struct resource *resource);
void lpc47n227_pnp_set_iobase(device_t dev, unsigned iobase);
void lpc47n227_pnp_set_drq(device_t dev, unsigned drq);
void lpc47n227_pnp_set_irq(device_t dev, unsigned irq);
void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase);
void lpc47n227_pnp_set_drq(device_t dev, u8 drq);
void lpc47n227_pnp_set_irq(device_t dev, u8 irq);
void lpc47n227_pnp_set_enable(device_t dev, int enable);
static void pnp_enter_conf_state(device_t dev);
static void pnp_exit_conf_state(device_t dev);
@ -64,10 +62,9 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
{ &ops, LPC47N227_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{&ops, LPC47N227_SP1, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},},
{&ops, LPC47N227_SP2, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},},
{&ops, LPC47N227_KBDC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0},
{0x7f8, 0x4},}
{ &ops, LPC47N227_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, LPC47N227_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, LPC47N227_KBDC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, },
};
/**
@ -86,6 +83,9 @@ static void enable_dev(device_t dev)
* Configure the specified Super I/O device with the resources (I/O space,
* etc.) that have been allocate for it.
*
* NOTE: Cannot use pnp_set_resources() here because it assumes chip
* support for logical devices, which the LPC47N227 doesn't have.
*
* @param dev Pointer to structure describing a Super I/O device.
*/
void lpc47n227_pnp_set_resources(device_t dev)
@ -93,44 +93,30 @@ void lpc47n227_pnp_set_resources(device_t dev)
struct resource *res;
pnp_enter_conf_state(dev);
/*
* NOTE: Cannot use pnp_set_resources() here because it assumes chip
* support for logical devices, which the LPC47N227 doesn't have.
*/
for (res = dev->resource_list; res; res = res->next)
lpc47n227_pnp_set_resource(dev, res);
pnp_exit_conf_state(dev);
}
void lpc47n227_pnp_enable_resources(device_t dev)
{
pnp_enter_conf_state(dev);
/*
* NOTE: Cannot use pnp_enable_resources() here because it assumes chip
* support for logical devices, which the LPC47N227 doesn't have.
*/
lpc47n227_pnp_set_enable(dev, 1);
pnp_exit_conf_state(dev);
}
void lpc47n227_pnp_enable(device_t dev)
void lpc47n227_pnp_enable_resources(device_t dev)
{
pnp_enter_conf_state(dev);
lpc47n227_pnp_set_enable(dev, 1);
pnp_exit_conf_state(dev);
}
/*
* NOTE: Cannot use pnp_set_enable() here because it assumes chip
* support for logical devices, which the LPC47N227 doesn't have.
*/
if (dev->enabled) {
lpc47n227_pnp_set_enable(dev, 1);
} else {
lpc47n227_pnp_set_enable(dev, 0);
}
void lpc47n227_pnp_enable(device_t dev)
{
pnp_enter_conf_state(dev);
lpc47n227_pnp_set_enable(dev, (dev->enabled) ? 1 : 0);
pnp_exit_conf_state(dev);
}
@ -155,12 +141,10 @@ static void lpc47n227_init(device_t dev)
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com1);
break;
case LPC47N227_SP2:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com2);
break;
case LPC47N227_KBDC:
printk(BIOS_DEBUG, "LPC47N227: Initializing keyboard.\n");
pc_keyboard_init(&conf->keyboard);
@ -176,7 +160,7 @@ static void lpc47n227_pnp_set_resource(device_t dev, struct resource *resource)
return;
}
/* Now store the resource */
/* Now store the resource. */
/*
* NOTE: Cannot use pnp_set_XXX() here because they assume chip
* support for logical devices, which the LPC47N227 doesn't have.
@ -197,7 +181,7 @@ static void lpc47n227_pnp_set_resource(device_t dev, struct resource *resource)
report_resource_stored(dev, resource, "");
}
void lpc47n227_pnp_set_iobase(device_t dev, unsigned iobase)
void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase)
{
ASSERT(!(iobase & 0x3));
@ -205,33 +189,29 @@ void lpc47n227_pnp_set_iobase(device_t dev, unsigned iobase)
case LPC47N227_PP:
pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff);
break;
case LPC47N227_SP1:
pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff);
break;
case LPC47N227_SP2:
pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff);
break;
case LPC47N227_KBDC:
break;
default:
BUG();
break;
}
}
void lpc47n227_pnp_set_drq(device_t dev, unsigned drq)
void lpc47n227_pnp_set_drq(device_t dev, u8 drq)
{
if (dev->path.pnp.device == LPC47N227_PP) {
const uint8_t PP_DMA_MASK = 0x0F;
const uint8_t PP_DMA_SELECTION_REGISTER = 0x26;
uint8_t current_config =
pnp_read_config(dev, PP_DMA_SELECTION_REGISTER);
uint8_t new_config;
const u8 PP_DMA_MASK = 0x0F;
const u8 PP_DMA_SELECTION_REGISTER = 0x26;
u8 current_config, new_config;
if (dev->path.pnp.device == LPC47N227_PP) {
current_config = pnp_read_config(dev,
PP_DMA_SELECTION_REGISTER);
ASSERT(!(drq & ~PP_DMA_MASK)); // DRQ out of range??
new_config = (current_config & ~PP_DMA_MASK) | drq;
pnp_write_config(dev, PP_DMA_SELECTION_REGISTER, new_config);
@ -240,33 +220,27 @@ void lpc47n227_pnp_set_drq(device_t dev, unsigned drq)
}
}
void lpc47n227_pnp_set_irq(device_t dev, unsigned irq)
void lpc47n227_pnp_set_irq(device_t dev, u8 irq)
{
uint8_t irq_config_register = 0;
uint8_t irq_config_mask = 0;
uint8_t current_config;
uint8_t new_config;
u8 irq_config_register = 0, irq_config_mask = 0;
u8 current_config, new_config;
switch (dev->path.pnp.device) {
case LPC47N227_PP:
irq_config_register = 0x27;
irq_config_mask = 0x0F;
break;
case LPC47N227_SP1:
irq_config_register = 0x28;
irq_config_mask = 0xF0;
irq <<= 4;
break;
case LPC47N227_SP2:
irq_config_register = 0x28;
irq_config_mask = 0x0F;
break;
case LPC47N227_KBDC:
break;
default:
BUG();
return;
@ -279,58 +253,46 @@ void lpc47n227_pnp_set_irq(device_t dev, unsigned irq)
void lpc47n227_pnp_set_enable(device_t dev, int enable)
{
uint8_t power_register = 0;
uint8_t power_mask = 0;
uint8_t current_power;
uint8_t new_power;
u8 power_register = 0, power_mask = 0, current_power, new_power;
switch (dev->path.pnp.device) {
case LPC47N227_PP:
power_register = 0x01;
power_mask = 0x04;
break;
case LPC47N227_SP1:
power_register = 0x02;
power_mask = 0x08;
break;
case LPC47N227_SP2:
power_register = 0x02;
power_mask = 0x80;
break;
case LPC47N227_KBDC:
break;
default:
BUG();
return;
}
current_power = pnp_read_config(dev, power_register);
new_power = current_power & ~power_mask; // disable by default
new_power = current_power & ~power_mask; /* Disable by default. */
if (enable) {
struct resource *ioport_resource =
find_resource(dev, PNP_IDX_IO0);
struct resource *ioport_resource;
ioport_resource = find_resource(dev, PNP_IDX_IO0);
lpc47n227_pnp_set_iobase(dev, ioport_resource->base);
new_power |= power_mask; // Enable
new_power |= power_mask; /* Enable. */
} else {
lpc47n227_pnp_set_iobase(dev, 0);
}
pnp_write_config(dev, power_register, new_power);
}
/** Enable access to the LPC47N227's configuration registers. */
static void pnp_enter_conf_state(device_t dev)
{
outb(0x55, dev->path.pnp.port);
}
/** Disable access to the LPC47N227's configuration registers. */
static void pnp_exit_conf_state(device_t dev)
{
outb(0xaa, dev->path.pnp.port);

1
src/superio/smsc/sio10n268/Makefile.inc
View File

@ -18,3 +18,4 @@
##
ramstage-$(CONFIG_SUPERIO_SMSC_SIO10N268) += sio10n268.c

9
src/superio/smsc/sio10n268/sio10n268.c
View File

@ -27,13 +27,10 @@
static void init(device_t dev)
{
struct superio_smsc_sio10n268_config *conf;
struct superio_smsc_sio10n268_config *conf = dev->chip_info;
if (!dev->enabled) {
if (!dev->enabled)
return;
}
conf = dev->chip_info;
switch (dev->path.pnp.device) {
case SIO10N268_FDC: /* TODO. */
@ -58,7 +55,7 @@ static struct device_operations ops = {
/* TODO: FDC, PP, AUX. */
static struct pnp_info pnp_dev_info[] = {
{ &ops, SIO10N268_KBDC, PNP_IO0 | PNP_IO1, { 0x7f8, 0 }, { 0x7f8, 0x4}, },
{ &ops, SIO10N268_KBDC, PNP_IO0 | PNP_IO1, {0x07f8, 0}, {0x07f8, 4}, },
};
static void enable_dev(struct device *dev)

1
src/superio/smsc/smscsuperio/Makefile.inc
View File

@ -19,3 +19,4 @@
##
ramstage-$(CONFIG_SUPERIO_SMSC_SMSCSUPERIO) += superio.c

4
src/superio/smsc/smscsuperio/smscsuperio_early_serial.c
View File

@ -33,9 +33,9 @@
* @param dev The device to use.
* @param iobase The I/O base of the serial port (usually 0x3f8/0x2f8).
*/
static inline void smscsuperio_enable_serial(device_t dev, uint16_t iobase)
static void smscsuperio_enable_serial(device_t dev, u16 iobase)
{
uint16_t port = dev >> 8;
u16 port = dev >> 8;
outb(0x55, port); /* Enter the configuration state. */
pnp_set_logical_device(dev);

42
src/superio/smsc/smscsuperio/superio.c
View File

@ -70,8 +70,8 @@
/* Static variables for the Super I/O device ID and revision. */
static int first_time = 1;
static uint8_t superio_id = 0;
static uint8_t superio_rev = 0;
static u8 superio_id = 0;
static u8 superio_rev = 0;
/**
* A list of all possible logical devices which may be supported by at least
@ -117,7 +117,7 @@ enum {
* The result would be that the init code would be executed twice!
*/
static const struct logical_devices {
uint8_t superio_id;
u8 superio_id;
int devs[MAX_LOGICAL_DEVICES];
} logical_device_table[] = {
/* Chip FDC PP SP1 SP2 RTC KBC AUX XBUS HWM GAME PME MPU RT ACPI SMB */
@ -150,7 +150,7 @@ static const struct logical_devices {
*
* @param dev The device to use.
*/
static inline void smsc_pnp_enter_conf_state(device_t dev)
static void smsc_pnp_enter_conf_state(device_t dev)
{
outb(0x55, dev->path.pnp.port);
}
@ -162,7 +162,7 @@ static inline void smsc_pnp_enter_conf_state(device_t dev)
*
* @param dev The device to use.
*/
static inline void smsc_pnp_exit_conf_state(device_t dev)
static void smsc_pnp_exit_conf_state(device_t dev)
{
outb(0xaa, dev->path.pnp.port);
}
@ -262,18 +262,17 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
{ &ops, LD_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, LD_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, LD_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, LD_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, LD_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, LD_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, LD_RTC, },
{ &ops, LD_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 },
{ 0x7ff, 4 },},
{ &ops, LD_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
{ &ops, LD_AUX, },
{ &ops, LD_XBUS, },
{ &ops, LD_HWM, PNP_IO0, { 0x7f0, 0 }, },
{ &ops, LD_HWM, PNP_IO0, {0x07f0, 0}, },
{ &ops, LD_GAME, },
{ &ops, LD_PME, },
{ &ops, LD_MPU401, },
{ &ops, LD_RT, PNP_IO0, { 0x780, 0 }, },
{ &ops, LD_RT, PNP_IO0, {0x0780, 0}, },
{ &ops, LD_ACPI, },
{ &ops, LD_SMB, },
};
@ -291,7 +290,7 @@ static void enable_dev(device_t dev)
{
int i, j, fn;
int tmp[MAX_LOGICAL_DEVICES];
uint8_t test7;
u8 test7;
if (first_time) {
/* Read the device ID and revision of the Super I/O chip. */
@ -302,20 +301,22 @@ static void enable_dev(device_t dev)
/* TODO: Error handling? */
printk(BIOS_INFO, "Found SMSC Super I/O (ID=0x%02x, rev=0x%02x)\n",
superio_id, superio_rev);
printk(BIOS_INFO, "Found SMSC Super I/O (ID=0x%02x, "
"rev=0x%02x)\n", superio_id, superio_rev);
first_time = 0;
if (superio_id == LPC47M172) {
/* Do not use the default logical device number
* but instead the standard smsc registers set
/*
* Do not use the default logical device number but
* instead the standard SMSC registers set.
*/
/* TEST7 configuration register (0x29)
* bit 0 : LD_NUM (0 = new, 1 = std smsc)
/*
* TEST7 configuration register (0x29)
* Bit 0: LD_NUM (0 = new, 1 = std SMSC)
*/
test7 = pnp_read_config(dev, DEVICE_TEST7_REG);
test7 |= 1;
test7 |= (1 << 0);
pnp_write_config(dev, DEVICE_TEST7_REG, test7);
}
}
@ -333,7 +334,8 @@ static void enable_dev(device_t dev)
for (j = 0; j < ARRAY_SIZE(pnp_dev_info); j++)
tmp[j] = pnp_dev_info[j].function;
/* Replace the LD_FOO markers in pnp_dev_info[] with
/*
* Replace the LD_FOO markers in pnp_dev_info[] with
* the real logical device IDs of this Super I/O chip.
*/
for (j = 0; j < ARRAY_SIZE(pnp_dev_info); j++) {

8
src/superio/winbond/w83627dhg/superio.c
View File

@ -96,16 +96,16 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
{ &ops, W83627DHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ff8, 0}, },
{ &ops, W83627DHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ff8, 0}, },
{ &ops, W83627DHG_SP1, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
{ &ops, W83627DHG_SP2, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
{ &ops, W83627DHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0xfff, 0 }, { 0xfff, 0x4}, },
{ &ops, W83627DHG_SP1, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, W83627DHG_SP2, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, W83627DHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x0fff, 0}, {0x0fff, 4}, },
/* the next line makes coreboot hang in pnp_enable_devices() */
/* { &ops, W83627DHG_SPI, PNP_IO1, { 0xff8, 0 }, }, */
{ &ops, W83627DHG_GPIO6, },
{ &ops, W83627DHG_WDTO_PLED, },
{ &ops, W83627DHG_GPIO2345, },
{ &ops, W83627DHG_ACPI, },
{ &ops, W83627DHG_HWM, PNP_IO0 | PNP_IRQ0, { 0xffe, 0 }, },
{ &ops, W83627DHG_HWM, PNP_IO0 | PNP_IRQ0, {0x0ffe, 0}, },
{ &ops, W83627DHG_PECI_SST, },
};

14
src/superio/winbond/w83627ehg/superio.c
View File

@ -180,15 +180,15 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
{ &ops, W83627EHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83627EHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83627EHG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, W83627EHG_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, W83627EHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
{ &ops, W83627EHG_SFI, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, W83627EHG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627EHG_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627EHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
{ &ops, W83627EHG_SFI, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627EHG_WDTO_PLED, },
{ &ops, W83627EHG_ACPI, },
{ &ops, W83627EHG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
{ &ops, W83627EHG_GAME, PNP_IO0, { 0x7ff, 0 }, },
{ &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 } , {0x7fe, 0x4}, },
{ &ops, W83627EHG_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, W83627EHG_GAME, PNP_IO0, {0x07ff, 0}, },
{ &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, {0x07ff, 0}, {0x07fe, 4}, },
{ &ops, W83627EHG_GPIO1, },
{ &ops, W83627EHG_GPIO2, },
{ &ops, W83627EHG_GPIO3, },

12
src/superio/winbond/w83627hf/superio.c
View File

@ -199,15 +199,15 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
{ &ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
{ &ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, },
{ &ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
{ &ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07ff, 0}, {0x07fe, 4}, },
{ &ops, W83627HF_GPIO2, },
{ &ops, W83627HF_GPIO3, },
{ &ops, W83627HF_ACPI, },
{ &ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
{ &ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
};
static void enable_dev(struct device *dev)

12
src/superio/winbond/w83627thf/superio.c
View File

@ -98,15 +98,15 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
{ &ops, W83627THF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83627THF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83627THF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, W83627THF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, W83627THF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
{ &ops, W83627THF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, W83627THF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4} },
{ &ops, W83627THF_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627THF_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627THF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
{ &ops, W83627THF_CIR, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627THF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07ff, 0}, {0x07fe, 4}, },
/* { W83627THF_GPIO2, }, */
/* { W83627THF_GPIO3, }, */
{ &ops, W83627THF_ACPI, PNP_IRQ0, },
{ &ops, W83627THF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } },
{ &ops, W83627THF_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
};
static void enable_dev(device_t dev)

10
src/superio/winbond/w83627thg/superio.c
View File

@ -97,14 +97,14 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
{ &ops, W83627THG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83627THG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83627THG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, W83627THG_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC1, { 0x7f8, 0 }, },
{ &ops, W83627THG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1 | PNP_MSC0, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
{ &ops, W83627THG_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4} },
{ &ops, W83627THG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627THG_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC1, {0x07f8, 0}, },
{ &ops, W83627THG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1 | PNP_MSC0, {0x07ff, 0}, {0x07ff, 4}, },
{ &ops, W83627THG_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07ff, 0}, {0x07fe, 4}, },
{ &ops, W83627THG_GPIO2, },
{ &ops, W83627THG_GPIO3, PNP_EN | PNP_MSC0 | PNP_MSC1, },
{ &ops, W83627THG_ACPI, PNP_IRQ0, },
{ &ops, W83627THG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } },
{ &ops, W83627THG_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
};
static void enable_dev(device_t dev)

16
src/superio/winbond/w83627uhg/superio.c
View File

@ -147,19 +147,19 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
{ &ops, W83627UHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83627UHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83627UHG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, W83627UHG_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, W83627UHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
{ &ops, W83627UHG_SP3, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, W83627UHG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627UHG_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627UHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
{ &ops, W83627UHG_SP3, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627UHG_GPIO3_4, },
{ &ops, W83627UHG_WDTO_PLED_GPIO5_6, },
{ &ops, W83627UHG_GPIO1_2, },
{ &ops, W83627UHG_ACPI, PNP_IRQ0, },
{ &ops, W83627UHG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } },
{ &ops, W83627UHG_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, W83627UHG_PECI_SST, },
{ &ops, W83627UHG_SP4, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, W83627UHG_SP5, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, W83627UHG_SP6, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, W83627UHG_SP4, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627UHG_SP5, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627UHG_SP6, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
};
static void enable_dev(device_t dev)

10
src/superio/winbond/w83697hf/superio.c
View File

@ -97,14 +97,14 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
{ &ops, W83697HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83697HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83697HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, W83697HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, W83697HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, W83697HF_GAME_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, },
{ &ops, W83697HF_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83697HF_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83697HF_CIR, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83697HF_GAME_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07ff, 0}, {0x07fe, 4}, },
{ &ops, W83697HF_MIDI_GPIO5, },
{ &ops, W83697HF_GPIO234, },
{ &ops, W83697HF_ACPI, },
{ &ops, W83697HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
{ &ops, W83697HF_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
};
static void enable_dev(struct device *dev)

18
src/superio/winbond/w83977f/superio.c
View File

@ -94,15 +94,15 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, W83977F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x7f8, 0 }, },
{ &ops, W83977F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x7f8, 0 }, },
{ &ops, W83977F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, W83977F_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, W83977F_RTC, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, W83977F_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7f8, 0 }, { 0x7f8, 0x0}, },
{ &ops, W83977F_IR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, W83977F_GPIO1, PNP_IO0, { 0x7f8, 0 }, },
{ &ops, W83977F_GPIO2, PNP_IO0, { 0x7f8, 0 }, },
{ &ops, W83977F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83977F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83977F_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83977F_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83977F_RTC, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83977F_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07f8, 0}, {0x07f8, 0}, },
{ &ops, W83977F_IR, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83977F_GPIO1, PNP_IO0, {0x07f8, 0}, },
{ &ops, W83977F_GPIO2, PNP_IO0, {0x07f8, 0}, },
};
static void enable_dev(device_t dev)

10
src/superio/winbond/w83977tf/superio.c
View File

@ -98,11 +98,11 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
{ &ops, W83977TF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83977TF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83977TF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, W83977TF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, W83977TF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
{ &ops, W83977TF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, W83977TF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4} },
{ &ops, W83977TF_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83977TF_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83977TF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
{ &ops, W83977TF_CIR, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83977TF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07ff, 0}, {0x07fe, 4}, },
{ &ops, W83977TF_ACPI, PNP_IRQ0, },
};