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arch/x86/exit_car.S: Make sure _cbmem_top_ptr hits dram 

INVD is called below so if postcar is running in a cached environment
it needs to happen.

NOTE: postcar cannot execute in a cached environment if clflush is not
supported!

Change-Id: I37681ee1f1d2ae5f9dd824b5baf7b23b2883b1dc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Arthur Heymans 2019-11-25 19:58:36 +01:00 committed by Patrick Georgi
parent 65605276a4
commit a6a2f9372c
2 changed files with 10 additions and 0 deletions
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8
src/arch/x86/exit_car.S
View File

@ -2,6 +2,7 @@
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/x86/cr.h> #include <cpu/x86/cr.h>
#include <cpu/x86/cache.h>
.section ".module_parameters", "aw", @progbits .section ".module_parameters", "aw", @progbits
/* stack_top indicates the stack to pull MTRR information from. */ /* stack_top indicates the stack to pull MTRR information from. */
@ -54,7 +55,14 @@ _start:
movl 4(%esp), %eax movl 4(%esp), %eax
movl %eax, _cbmem_top_ptr movl %eax, _cbmem_top_ptr
#endif #endif
/* Make sure _cbmem_top_ptr hits dram before invd */
movl $1, %eax
cpuid
btl $CPUID_FEATURE_CLFLUSH_BIT, %edx
jz skip_clflush
clflush _cbmem_top_ptr
skip_clflush:
/* chipset_teardown_car() is expected to disable cache-as-ram. */ /* chipset_teardown_car() is expected to disable cache-as-ram. */
call chipset_teardown_car call chipset_teardown_car

2
src/include/cpu/x86/cache.h
View File

@ -8,6 +8,8 @@
#define CR0_CacheDisable (CR0_CD) #define CR0_CacheDisable (CR0_CD)
#define CR0_NoWriteThrough (CR0_NW) #define CR0_NoWriteThrough (CR0_NW)
#define CPUID_FEATURE_CLFLUSH_BIT 19
#if !defined(__ASSEMBLER__) #if !defined(__ASSEMBLER__)
static inline void wbinvd(void) static inline void wbinvd(void)