diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index b8c990e631..1355096abe 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -51,6 +51,9 @@ static inline unsigned int cpuid_get_max_func(void)
 #define CPUID_FEATURE_PSE36 (1 << 17)
 #define CPUID_FEAURE_HTT (1 << 28)
 
+/* Structured Extended Feature Flags */
+#define CPUID_STRUCT_EXTENDED_FEATURE_FLAGS 0x7
+
 // Intel leaf 0x4, AMD leaf 0x8000001d EAX
 
 #define CPUID_CACHE(x, res) \
diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc
index de56a3a1e6..c4ac57ebcf 100644
--- a/src/cpu/intel/common/Makefile.inc
+++ b/src/cpu/intel/common/Makefile.inc
@@ -1,5 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
+romstage-$(CONFIG_CPU_INTEL_COMMON) += common_init.c
 ramstage-$(CONFIG_CPU_INTEL_COMMON) += common_init.c
 ramstage-$(CONFIG_CPU_INTEL_COMMON) += hyperthreading.c
 ramstage-$(CONFIG_CPU_INTEL_COMMON_VOLTAGE) += voltage.c
diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h
index a29fd2e6b6..d28d95c5c8 100644
--- a/src/cpu/intel/common/common.h
+++ b/src/cpu/intel/common/common.h
@@ -66,4 +66,12 @@ void set_energy_perf_pref(u8 pref);
  */
 void enable_energy_perf_pref(void);
 
+/*
+ * Check if Total Memory Encryption (TME) is supported by the CPU
+ *
+ * coreboot shall detect the existence of TME feature by running CPUID instruction:
+ * CPUID leaf 7/sub-leaf 0: Return Value in ECX [bit 13] = 1
+ */
+bool is_tme_supported(void);
+
 #endif
diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c
index b24f742476..f8608ae029 100644
--- a/src/cpu/intel/common/common_init.c
+++ b/src/cpu/intel/common/common_init.c
@@ -14,6 +14,9 @@
 #define  CPUID_6_ENGERY_PERF_PREF	(1 << 10)
 #define  CPUID_6_HWP			(1 << 7)
 
+/* Structured Extended Feature Flags */
+#define CPUID_EXT_FEATURE_TME_SUPPORTED (1 << 13)
+
 void set_vmx_and_lock(void)
 {
 	set_feature_ctrl_vmx();
@@ -227,3 +230,11 @@ void set_energy_perf_pref(u8 pref)
 	msr_unset_and_set(IA32_HWP_REQUEST, IA32_HWP_REQUEST_EPP_MASK,
 		(uint64_t)pref << IA32_HWP_REQUEST_EPP_SHIFT);
 }
+
+bool is_tme_supported(void)
+{
+	struct cpuid_result cpuid_regs;
+
+	cpuid_regs = cpuid_ext(CPUID_STRUCT_EXTENDED_FEATURE_FLAGS, 0x0);
+	return (cpuid_regs.ecx & CPUID_EXT_FEATURE_TME_SUPPORTED);
+}
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 4fc4099734..84f83e3bbe 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -3,6 +3,7 @@
 #include <assert.h>
 #include <console/console.h>
 #include <cpu/x86/msr.h>
+#include <cpu/intel/common/common.h>
 #include <cpu/intel/cpu_ids.h>
 #include <device/device.h>
 #include <drivers/wifi/generic/wifi.h>
diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c
index c317e05854..bf361a4791 100644
--- a/src/soc/intel/common/block/cpu/cpulib.c
+++ b/src/soc/intel/common/block/cpu/cpulib.c
@@ -19,7 +19,6 @@
 #define CPUID_HYBRID_INFORMATION		0x1a
 
 /* Structured Extended Feature Flags */
-#define CPUID_STRUCT_EXTENDED_FEATURE_FLAGS	0x7
 #define HYBRID_FEATURE				BIT(15)
 
 /*
@@ -485,15 +484,6 @@ void init_core_prmrr(void)
 		sync_core_prmrr();
 }
 
-bool is_tme_supported(void)
-{
-	struct cpuid_result cpuid_regs;
-
-	/* ECX[13] is feature capability */
-	cpuid_regs = cpuid_ext(CPUID_STRUCT_EXTENDED_FEATURE_FLAGS, 0x0);
-	return (cpuid_regs.ecx & TME_SUPPORTED);
-}
-
 void set_tme_core_activate(void)
 {
 	msr_t msr = { .lo = 0, .hi = 0 };
diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h
index cbc9e449de..5601d5d067 100644
--- a/src/soc/intel/common/block/include/intelblocks/cpulib.h
+++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h
@@ -190,14 +190,6 @@ void enable_pm_timer_emulation(void);
  */
 void init_core_prmrr(void);
 
-/*
- * Check if TME is supported by the CPU
- *
- * coreboot shall detect the existence of TME feature by running CPUID instruction:
- * CPUID leaf 7/sub-leaf 0: Return Value in ECX [bit 13] = 1
- */
-bool is_tme_supported(void);
-
 /*
  * Set TME core activate MSR
  *
diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index 36aa11e623..2a07753abc 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -2,6 +2,7 @@
 
 #include <assert.h>
 #include <console/console.h>
+#include <cpu/intel/common/common.h>
 #include <cpu/intel/cpu_ids.h>
 #include <cpu/x86/msr.h>
 #include <device/device.h>
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index dd771655f2..afcbf2f711 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -2,6 +2,7 @@
 
 #include <assert.h>
 #include <console/console.h>
+#include <cpu/intel/common/common.h>
 #include <cpu/intel/cpu_ids.h>
 #include <cpu/x86/msr.h>
 #include <device/device.h>