GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

nb/intel/i945: Define and use MMCONF_BUS_NUMBER 

Change-Id: I5c75409fd3b7b018e402c471cbd856eca20278b7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49757
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2021-01-20 13:00:02 +01:00
parent 1ac6f8b804
commit a6b0922aa1
6 changed files with 21 additions and 60 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/northbridge/intel/i945/Kconfig
View File

@ -41,6 +41,10 @@ config I945_LVDS
config MMCONF_BASE_ADDRESS
default 0xf0000000
config MMCONF_BUS_NUMBER
int
default 64
config OVERRIDE_CLOCK_DISABLE
bool
default n

12
src/northbridge/intel/i945/acpi.c
View File

@ -1,24 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <types.h>
#include <acpi/acpi.h>
#include <acpi/acpigen.h>
#include <commonlib/helpers.h>
#include <device/device.h>
#include <device/pci_ops.h>
#include "i945.h"
unsigned long acpi_fill_mcfg(unsigned long current)
{
u32 length, pciexbar;
if (!decode_pcie_bar(&pciexbar, &length))
return current;
const int max_buses = length / MiB;
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
pciexbar, 0x0, 0x0, max_buses - 1);
CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1);
return current;
}

2
src/northbridge/intel/i945/acpi/i945.asl
View File

@ -42,7 +42,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

16
src/northbridge/intel/i945/bootblock.c
View File

@ -1,13 +1,23 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/bootblock.h>
#include <assert.h>
#include <device/pci_ops.h>
#include <types.h>
#include "i945.h"
static uint32_t encode_pciexbar_length(void)
{
switch (CONFIG_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 1 << 1;
case 64: return 2 << 1;
default: return dead_code_t(uint32_t);
}
}
void bootblock_early_northbridge_init(void)
{
uint32_t reg;
/*
* The "io" variant of the config access is explicitly used to setup the PCIEXBAR
* because CONFIG(MMCONF_SUPPORT) is set to true. That way all subsequent non-explicit
@ -17,6 +27,6 @@ void bootblock_early_northbridge_init(void)
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
*/
reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg);
}

2
src/northbridge/intel/i945/i945.h
View File

@ -353,8 +353,6 @@ void sdram_dump_mchbar_registers(void);
u32 decode_igd_memory_size(u32 gms);
u32 decode_tseg_size(const u8 esmramc);
int decode_pcie_bar(u32 *const base, u32 *const len);
/* Romstage mainboard callbacks */
/* Optional: Override the default LPC config. */
void mainboard_lpc_decode(void);

43
src/northbridge/intel/i945/northbridge.c
View File

@ -12,38 +12,6 @@
#include <cpu/intel/smm_reloc.h>
#include "i945.h"
int decode_pcie_bar(u32 *const base, u32 *const len)
{
*base = 0;
*len = 0;
struct device *dev = pcidev_on_root(0, 0);
if (!dev)
return 0;
const u32 pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
if (!(pciexbar_reg & (1 << 0)))
return 0;
switch ((pciexbar_reg >> 1) & 3) {
case 0: /* 256MB */
*base = pciexbar_reg & (0x0f << 28);
*len = 256 * MiB;
return 1;
case 1: /* 128M */
*base = pciexbar_reg & (0x1f << 27);
*len = 128 * MiB;
return 1;
case 2: /* 64M */
*base = pciexbar_reg & (0x3f << 26);
*len = 64 * MiB;
return 1;
}
return 0;
}
static void mch_domain_read_resources(struct device *dev)
{
uint32_t pci_tolm, tseg_sizek, cbmem_topk, delta_cbmem;
@ -153,9 +121,6 @@ void northbridge_write_smram(u8 smram)
pci_write_config8(dev, SMRAM, smram);
}
/* TODO We could determine how many PCIe busses we need in
* the bar. For now that number is hardcoded to a max of 64.
*/
static struct device_operations pci_domain_ops = {
.read_resources = mch_domain_read_resources,
.set_resources = mch_domain_set_resources,
@ -165,15 +130,9 @@ static struct device_operations pci_domain_ops = {
static void mc_read_resources(struct device *dev)
{
u32 pcie_config_base, pcie_config_len;
pci_dev_read_resources(dev);
if (decode_pcie_bar(&pcie_config_base, &pcie_config_len)) {
const int buses = pcie_config_len / MiB;
struct resource *resource = new_resource(dev, PCIEXBAR);
mmconf_resource_init(resource, pcie_config_base, buses);
}
mmconf_resource(dev, PCIEXBAR);
}
static struct device_operations mc_ops = {