soc/intel/tigerlake: Enable CNVi through dev_enabled

Check for dev enabled status for CNVi and update the
UPD accordingly.

BUG=none
BRANCH=none
TEST=Build and boot tglrvp

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I15a03cc70f12e094badf942dd81f22bd09531051
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Srinidhi N Kaushik 2020-03-12 01:15:43 -07:00 committed by Patrick Georgi
parent 4b9fa2d6ea
commit a6bff2d8ab
2 changed files with 5 additions and 6 deletions

View File

@ -222,10 +222,6 @@ struct soc_intel_tigerlake_config {
/* Enable Pch iSCLK */
uint8_t pch_isclk;
/* CNVi */
uint8_t CnviMode;
uint8_t CnviBtCore;
/* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
enum {
FORCE_DISABLE,

View File

@ -174,8 +174,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchLanEnable = dev->enabled;
/* CNVi */
params->CnviMode = config->CnviMode;
params->CnviBtCore = config->CnviBtCore;
dev = pcidev_path_on_root(PCH_DEVFN_CNVI_WIFI);
if (dev)
params->CnviMode = dev->enabled;
else
params->CnviMode = 0;
/* Legacy 8254 timer support */
params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;