ryu: Add TPS65913 regs/init for VDD_CPU 1.0V
Other default slams should be added later to the init table once we know what the kernel touches. But for now, only VDD_CPU is needed. Also slipped in a minor name change in mainboard.c BRANCH=none BUG=none TEST=none, no HW here for me to test on yet Change-Id: Ifbe86192449ed0466085808a0a12a15a7b6a1795 Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-on: https://chromium-review.googlesource.com/208385 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 53b332fb12cd685fbec265695333a70c4064524c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8645 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Tom Warren
Marc Jones
parent
2525885576
commit
a6ca9353a8
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@ -30,6 +30,6 @@ static void mainboard_enable(device_t dev)
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}
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struct chip_operations mainboard_ops = {
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.name = "rush",
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.name = "rush_ryu",
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.enable_dev = mainboard_enable,
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};
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@ -23,45 +23,31 @@
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#include <device/i2c.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include "boardid.h"
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#include "pmic.h"
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#include "reset.h"
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/* A44/Ryu has a TI 65913 PMIC on bus 4 (PWR_I2C) */
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enum {
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AS3722_I2C_ADDR = 0x40
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TI65913_I2C_ADDR = 0x58
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};
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struct as3722_init_reg {
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struct ti65913_init_reg {
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u8 reg;
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u8 val;
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u8 delay;
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};
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static struct as3722_init_reg init_list[] = {
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{AS3722_SDO0, 0x3C, 1},
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{AS3722_SDO1, 0x32, 0},
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{AS3722_LDO3, 0x59, 0},
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{AS3722_SDO2, 0x3C, 0},
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{AS3722_SDO3, 0x00, 0},
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{AS3722_SDO4, 0x00, 0},
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{AS3722_SDO5, 0x50, 0},
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{AS3722_SDO6, 0x28, 1},
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{AS3722_LDO0, 0x8A, 0},
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{AS3722_LDO1, 0x00, 0},
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{AS3722_LDO2, 0x10, 0},
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{AS3722_LDO4, 0x00, 0},
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{AS3722_LDO5, 0x00, 0},
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{AS3722_LDO6, 0x00, 0},
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{AS3722_LDO7, 0x00, 0},
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{AS3722_LDO9, 0x00, 0},
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{AS3722_LDO10, 0x00, 0},
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{AS3722_LDO11, 0x00, 1},
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static struct ti65913_init_reg init_list[] = {
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//TODO(twarren@nvidia.com): Add slams back to defaults
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// {TI65913_SMPS12_CTRL, 0x01, 0},
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// {TI65913_SMPS12_VOLTAGE, 0x38, 0},
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//etc.
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};
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static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay)
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{
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if (i2c_writeb(bus, AS3722_I2C_ADDR, reg, val)) {
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if (i2c_writeb(bus, TI65913_I2C_ADDR, reg, val)) {
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printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
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__func__, reg, val);
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/* Reset the SoC on any PMIC write error */
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@ -75,38 +61,23 @@ static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay)
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static void pmic_slam_defaults(unsigned bus)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(init_list); i++) {
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struct as3722_init_reg *reg = &init_list[i];
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struct ti65913_init_reg *reg = &init_list[i];
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pmic_write_reg(bus, reg->reg, reg->val, reg->delay);
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}
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}
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void pmic_init(unsigned bus)
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{
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/*
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* Don't need to set up VDD_CORE - already done - by OTP
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* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
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* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
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*/
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/* Don't need to set up VDD_CORE - already done - by EC ?? */
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/* Restore PMIC POR defaults, in case kernel changed 'em */
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pmic_slam_defaults(bus);
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/* SDO0: Set VDD_CPU to 1.2V. */
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pmic_write_reg(bus, 0x00, 0x50, 1);
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/* SDO6: Set VDD_GPU to 1.0V. */
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pmic_write_reg(bus, 0x06, 0x28, 1);
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/* LDO2: Set +1.2V_GEN_AVDD to 1.2V */
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pmic_write_reg(bus, 0x12, 0x10, 1);
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/*
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* Panel power GPIO O4. Set mode for GPIO4 (0x0c to 7), then set
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* the value (register 0x20 bit 4)
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*/
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pmic_write_reg(bus, 0x0c, 0x07, 0);
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pmic_write_reg(bus, 0x20, 0x10, 1);
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/* A44: Set VDD_CPU to 1.0V. */
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pmic_write_reg(bus, TI65913_SMPS12_CTRL, 0x01, 1);
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pmic_write_reg(bus, TI65913_SMPS12_VOLTAGE, 0x38, 0);
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printk(BIOS_DEBUG, "PMIC init done\n");
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}
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@ -17,32 +17,75 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __MAINBOARD_GOOGLE_RUSH_PMIC_H__
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#define __MAINBOARD_GOOGLE_RUSH_PMIC_H__
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#ifndef __MAINBOARD_GOOGLE_RUSH_RYU_PMIC_H__
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#define __MAINBOARD_GOOGLE_RUSH_RYU_PMIC_H__
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/* A44/Ryu has a TI 65913 PMIC */
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enum {
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AS3722_SDO0 = 0,
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AS3722_SDO1,
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AS3722_SDO2,
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AS3722_SDO3,
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AS3722_SDO4,
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AS3722_SDO5,
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AS3722_SDO6,
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TI65913_SMPS12_CTRL = 0x20,
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TI65913_SMPS12_TSTEP,
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TI65913_SMPS12_FORCE,
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TI65913_SMPS12_VOLTAGE,
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AS3722_LDO0 = 0x10,
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AS3722_LDO1,
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AS3722_LDO2,
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AS3722_LDO3,
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AS3722_LDO4,
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AS3722_LDO5,
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AS3722_LDO6,
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AS3722_LDO7,
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TI65913_SMPS3_CTRL,
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TI65913_SMPS3_VOLTAGE = 0x27,
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AS3722_LDO9 = 0x19,
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AS3722_LDO10,
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AS3722_LDO11,
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TI65913_SMPS45_CTRL = 0x28,
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TI65913_SMPS45_TSTEP,
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TI65913_SMPS45_FORCE,
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TI65913_SMPS45_VOLTAGE,
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TI65913_SMPS6_CTRL = 0x2C,
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TI65913_SMPS6_TSTEP,
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TI65913_SMPS6_FORCE,
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TI65913_SMPS6_VOLTAGE,
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TI65913_SMPS7_CTRL = 0x30,
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TI65913_SMPS7_VOLTAGE = 0x33,
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TI65913_SMPS8_CTRL = 0x34,
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TI65913_SMPS8_TSTEP,
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TI65913_SMPS8_FORCE,
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TI65913_SMPS8_VOLTAGE,
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TI65913_SMPS9_CTRL = 0x38,
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TI65913_SMPS9_VOLTAGE = 0x3B,
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TI65913_SMPS10_CTRL = 0x3C,
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TI65913_SMPS10_STATUS = 0x3F,
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TI65913_LDO1_CTRL = 0x50,
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TI65913_LDO1_VOLTAGE,
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TI65913_LDO2_CTRL,
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TI65913_LDO2_VOLTAGE,
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TI65913_LDO3_CTRL,
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TI65913_LDO3_VOLTAGE,
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TI65913_LDO4_CTRL,
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TI65913_LDO4_VOLTAGE,
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TI65913_LDO5_CTRL,
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TI65913_LDO5_VOLTAGE,
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TI65913_LDO6_CTRL,
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TI65913_LDO6_VOLTAGE,
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TI65913_LDO7_CTRL,
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TI65913_LDO7_VOLTAGE,
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TI65913_LDO8_CTRL,
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TI65913_LDO8_VOLTAGE,
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TI65913_LDO9_CTRL,
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TI65913_LDO9_VOLTAGE,
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TI65913_LDOLN_CTRL = 0x62,
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TI65913_LDOLN_VOLTAGE = 0x63,
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TI65913_LDOUSB_CTRL = 0x64,
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TI65913_LDOUSB_VOLTAGE = 0x65,
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TI65913_LDO_CTRL = 0x6A,
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TI65913_LDO_PD_CTRL1 = 0x6B,
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TI65913_LDO_PD_CTRL2 = 0x6C,
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TI65913_LDO_SHORT_STATUS1 = 0x6D,
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TI65913_LDO_SHORT_STATUS2 = 0x6E,
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};
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void pmic_init(unsigned bus);
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#endif /* __MAINBOARD_GOOGLE_RUSH_PMIC_H__ */
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#endif /* __MAINBOARD_GOOGLE_RUSH_RYU_PMIC_H__ */
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