soc/mediatek: Unify PLL function names
For consistency with the PLL function naming: - Rename edp_mux_set_sel() to mt_pll_edp_mux_set_sel(). - Rename mux_set_sel() to pll_mux_set_sel(). BUG=none TEST=build pass. BRANCH=corsola Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ifc7b14bf0db5a5461037e2fbf41756d1542ca945 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68622 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -64,14 +64,17 @@ DEFINE_BITFIELD(PLL_POWER_ISO_ENABLE, 1, 0)
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DEFINE_BITFIELD(PLL_CON1, 31, 0)
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DEFINE_BITFIELD(PLL_CON1, 31, 0)
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/* PLL internal interface */
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void pll_set_pcw_change(const struct pll *pll);
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void pll_set_pcw_change(const struct pll *pll);
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void mux_set_sel(const struct mux *mux, u32 sel);
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void pll_mux_set_sel(const struct mux *mux, u32 sel);
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int pll_set_rate(const struct pll *pll, u32 rate);
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int pll_set_rate(const struct pll *pll, u32 rate);
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/* PLL internal interface */
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void mt_pll_init(void);
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void mt_pll_init(void);
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void mt_pll_raise_little_cpu_freq(u32 freq);
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void mt_pll_raise_little_cpu_freq(u32 freq);
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void mt_pll_raise_cci_freq(u32 freq);
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void mt_pll_raise_cci_freq(u32 freq);
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void mt_pll_set_tvd_pll1_freq(u32 freq);
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void mt_pll_set_tvd_pll1_freq(u32 freq);
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void edp_mux_set_sel(u32 sel);
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void mt_pll_edp_mux_set_sel(u32 sel);
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void mt_pll_spmi_mux_select(void);
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void mt_pll_spmi_mux_select(void);
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void mt_pll_set_usb_clock(void);
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void mt_pll_set_usb_clock(void);
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@ -5,7 +5,7 @@
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#include <soc/pll.h>
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#include <soc/pll.h>
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#include <types.h>
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#include <types.h>
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void mux_set_sel(const struct mux *mux, u32 sel)
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void pll_mux_set_sel(const struct mux *mux, u32 sel)
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{
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{
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u32 mask = GENMASK(mux->mux_width - 1, 0);
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u32 mask = GENMASK(mux->mux_width - 1, 0);
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u32 val = read32(mux->reg);
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u32 val = read32(mux->reg);
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@ -347,7 +347,7 @@ void mt_pll_init(void)
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* TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!
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* TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!
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*************/
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*************/
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for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
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for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
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mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
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pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
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/* enable scpsys clock off control */
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/* enable scpsys clock off control */
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write32(&mtk_topckgen->clk_scp_cfg_0,
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write32(&mtk_topckgen->clk_scp_cfg_0,
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@ -445,5 +445,5 @@ void mt_mem_pll_config_post(void)
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void mt_mem_pll_mux(void)
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void mt_mem_pll_mux(void)
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{
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{
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/* CLK_CFG_0 */
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/* CLK_CFG_0 */
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mux_set_sel(&muxes[TOP_MEM_SEL], 1); /* 1: dmpll_ck */
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pll_mux_set_sel(&muxes[TOP_MEM_SEL], 1); /* 1: dmpll_ck */
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}
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}
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@ -344,7 +344,7 @@ void mt_pll_init(void)
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* TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!
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* TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!
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*/
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*/
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for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
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for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
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mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
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pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
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/* enable [14] dramc_pll104m_ck */
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/* enable [14] dramc_pll104m_ck */
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setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14);
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setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14);
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@ -468,7 +468,7 @@ void mt_pll_init(void)
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INFRACFG_AO_PERI_BUS_REG0_2, 1);
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INFRACFG_AO_PERI_BUS_REG0_2, 1);
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for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
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for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
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mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
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pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
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/* [4] SCP_CORE_CK_CG, [5] SEJ_CG */
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/* [4] SCP_CORE_CK_CG, [5] SEJ_CG */
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write32(&mt8186_infracfg_ao->module_sw_cg_0_clr, 0x00000030);
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write32(&mt8186_infracfg_ao->module_sw_cg_0_clr, 0x00000030);
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@ -528,7 +528,7 @@ void mt_pll_set_usb_clock(void)
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void mt_pll_spmi_mux_select(void)
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void mt_pll_spmi_mux_select(void)
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{
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{
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/* 4: ulposc1_d10 */
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/* 4: ulposc1_d10 */
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mux_set_sel(&muxes[TOP_SPMI_MST_SEL], 4);
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pll_mux_set_sel(&muxes[TOP_SPMI_MST_SEL], 4);
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}
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}
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u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id)
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u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id)
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@ -573,7 +573,7 @@ void mt_pll_init(void)
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* TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!
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* TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!
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*/
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*/
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for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
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for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
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mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
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pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
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/* turn off unused clock in infra_ao */
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/* turn off unused clock in infra_ao */
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write32(&mt8188_infracfg_ao->module_sw_cg_1_set, 0x00004000);
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write32(&mt8188_infracfg_ao->module_sw_cg_1_set, 0x00004000);
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@ -633,9 +633,9 @@ void mt_pll_set_tvd_pll1_freq(u32 freq)
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udelay(PLL_EN_DELAY);
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udelay(PLL_EN_DELAY);
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}
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}
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void edp_mux_set_sel(u32 sel)
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void mt_pll_edp_mux_set_sel(u32 sel)
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{
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{
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mux_set_sel(&muxes[TOP_EDP_SEL], sel);
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pll_mux_set_sel(&muxes[TOP_EDP_SEL], sel);
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}
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}
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void mt_pll_set_usb_clock(void)
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void mt_pll_set_usb_clock(void)
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@ -464,7 +464,7 @@ void mt_pll_init(void)
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* TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!
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* TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!
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*/
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*/
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for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
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for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
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mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
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pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
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/* enable [14] dramc_pll104m_ck */
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/* enable [14] dramc_pll104m_ck */
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setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14);
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setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14);
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@ -221,7 +221,7 @@ static int mtk_dpintf_power_on(struct mtk_dpintf *dpintf, const struct edid *edi
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pll_rate = edid->mode.pixel_clock * 1000 * (1 << ((clksrc + 1) / 2));
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pll_rate = edid->mode.pixel_clock * 1000 * (1 << ((clksrc + 1) / 2));
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mt_pll_set_tvd_pll1_freq(pll_rate / 4);
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mt_pll_set_tvd_pll1_freq(pll_rate / 4);
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edp_mux_set_sel(clksrc);
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mt_pll_edp_mux_set_sel(clksrc);
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mtk_dpintf_enable(dpintf);
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mtk_dpintf_enable(dpintf);
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@ -755,7 +755,7 @@ void mt_pll_init(void)
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* TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!
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* TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!
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*/
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*/
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for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
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for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
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mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
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pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
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/* switch sram control to bypass mode for PCIE_MAC_P0 */
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/* switch sram control to bypass mode for PCIE_MAC_P0 */
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setbits32(&mtk_spm->ap_mdsrc_req, 0x1);
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setbits32(&mtk_spm->ap_mdsrc_req, 0x1);
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@ -827,9 +827,9 @@ void mt_pll_set_tvd_pll1_freq(u32 freq)
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udelay(PLL_EN_DELAY);
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udelay(PLL_EN_DELAY);
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}
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}
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void edp_mux_set_sel(u32 sel)
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void mt_pll_edp_mux_set_sel(u32 sel)
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{
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{
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mux_set_sel(&muxes[TOP_EDP_SEL], sel);
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pll_mux_set_sel(&muxes[TOP_EDP_SEL], sel);
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}
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}
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u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id)
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u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id)
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