nb/intel/gm45: Remove the C native graphic init
Libgfxinit provides a better alternative to the native C init. While libgfxinit mandates an ada compiler, we want to encourage use of it since it is in much better shape and is actually maintained. This way libgfxinit also gets build-tested by Jenkins. Change-Id: I540cf08cef6ff7825694ebfa36e2e6437916e657 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/27016 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans
Patrick Georgi
parent
3c86293dc1
commit
a6ce5d3faa
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@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS
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select HAVE_OPTION_TABLE
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select HAVE_CMOS_DEFAULT
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select HAVE_ACPI_RESUME
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select MAINBOARD_HAS_NATIVE_VGA_INIT
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select INTEL_INT15
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select SUPERIO_NSC_PC87382
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select SUPERIO_NSC_PC87384
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@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS
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select HAVE_OPTION_TABLE
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select HAVE_CMOS_DEFAULT
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select HAVE_ACPI_RESUME
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select MAINBOARD_HAS_NATIVE_VGA_INIT
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select INTEL_INT15
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select SUPERIO_NSC_PC87382
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select DRIVERS_LENOVO_WACOM
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@ -26,8 +26,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
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select INTEL_EDID
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select INTEL_GMA_ACPI
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select INTEL_GMA_SSC_ALTERNATE_REF
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select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
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select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
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select POSTCAR_STAGE
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select POSTCAR_CONSOLE
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select SMM_TSEG
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@ -29,16 +29,10 @@
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#include "drivers/intel/gma/i915_reg.h"
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#include "chip.h"
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#include "gm45.h"
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#include <drivers/intel/gma/intel_bios.h>
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#include <drivers/intel/gma/edid.h>
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#include <drivers/intel/gma/i915.h>
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#include <drivers/intel/gma/opregion.h>
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#include <pc80/vga.h>
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#include <pc80/vga_io.h>
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#include <drivers/intel/gma/libgfxinit.h>
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#define BASE_FREQUENCY 96000
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static struct resource *gtt_res = NULL;
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u32 gtt_read(u32 reg)
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@ -64,579 +58,6 @@ void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
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gnvs_ptr->aslb = aslb;
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}
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static void gma_init_lvds(const struct northbridge_intel_gm45_config *info,
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u8 *mmio, u32 physbase, u16 piobase, u32 lfb,
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struct edid *edid)
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{
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int i;
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struct edid_mode *mode;
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u32 hactive, vactive, right_border, bottom_border;
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int hpolarity, vpolarity;
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u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch;
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u32 smallest_err = 0xffffffff;
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u32 target_frequency;
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u32 pixel_p1 = 1;
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u32 pixel_n = 1;
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u32 pixel_m1 = 1;
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u32 pixel_m2 = 1;
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u32 pixel_p2;
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vga_gr_write(0x18, 0);
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/* Setup GTT. */
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for (i = 0; i < 0x2000; i++)
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{
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outl((i << 2) | 1, piobase);
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outl(physbase + (i << 12) + 1, piobase + 4);
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}
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write32(mmio + ADPA, 0x40008c18);
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write32(mmio + 0x7041c, 0x0);
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write32(mmio + _DPLL_B_MD, 0x3);
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vga_misc_write(0x67);
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const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
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0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
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0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,
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0xff
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};
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vga_cr_write(0x11, 0);
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for (i = 0; i <= 0x18; i++)
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vga_cr_write(i, cr[i]);
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/* Disable screen memory to prevent garbage from appearing. */
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vga_sr_write(1, vga_sr_read(1) | 0x20);
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mode = &edid->mode;
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hactive = edid->x_resolution;
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vactive = edid->y_resolution;
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right_border = mode->hborder;
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bottom_border = mode->vborder;
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hpolarity = (mode->phsync == '-');
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vpolarity = (mode->pvsync == '-');
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vsync = mode->vspw;
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hsync = mode->hspw;
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vblank = mode->vbl;
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hblank = mode->hbl;
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hfront_porch = mode->hso;
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vfront_porch = mode->vso;
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if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
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vga_sr_write(1, 1);
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vga_sr_write(0x2, 0xf);
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vga_sr_write(0x3, 0x0);
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vga_sr_write(0x4, 0xe);
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vga_gr_write(0, 0x0);
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vga_gr_write(1, 0x0);
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vga_gr_write(2, 0x0);
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vga_gr_write(3, 0x0);
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vga_gr_write(4, 0x0);
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vga_gr_write(5, 0x0);
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vga_gr_write(6, 0x5);
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vga_gr_write(7, 0xf);
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vga_gr_write(0x10, 0x1);
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vga_gr_write(0x11, 0);
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edid->bytes_per_line = (edid->bytes_per_line + 63) & ~63;
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write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
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write32(mmio + DSPADDR(0), 0);
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write32(mmio + DSPSTRIDE(0), edid->bytes_per_line);
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write32(mmio + DSPSURF(0), 0);
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for (i = 0; i < 0x100; i++)
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write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
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} else {
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vga_textmode_init();
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}
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target_frequency = mode->pixel_clock;
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/*
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* p2 divisor must 7 for dual channel LVDS
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* and 14 for single channel LVDS
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*/
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pixel_p2 = mode->lvds_dual_channel ? 7 : 14;
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/*
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* Find suitable divisors, m1, m2, p1, n.
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* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2
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* should be closest to target frequency as possible
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*/
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u32 candn, candm1, candm2, candp1;
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for (candn = 1; candn <= 3; candn++) {
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for (candm1 = 23; candm1 >= 17; candm1--) {
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for (candm2 = 11; candm2 >= 5; candm2--) {
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for (candp1 = mode->lvds_dual_channel ? 6 : 8;
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candp1 >= 2; candp1--) {
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u32 m = 5 * (candm1 + 2) + (candm2 + 2);
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u32 p = candp1 * pixel_p2;
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u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2);
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u32 dot = DIV_ROUND_CLOSEST(vco, p);
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u32 this_err = MAX(dot, target_frequency) -
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MIN(dot, target_frequency);
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if (this_err < smallest_err) {
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smallest_err = this_err;
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pixel_n = candn;
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pixel_m1 = candm1;
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pixel_m2 = candm2;
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pixel_p1 = candp1;
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}
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}
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}
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}
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}
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if (smallest_err == 0xffffffff) {
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printk (BIOS_ERR, "Couldn't find GFX clock divisors\n");
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return;
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}
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printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
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hactive, vactive);
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printk(BIOS_DEBUG, "Borders %d x %d\n",
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right_border, bottom_border);
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printk(BIOS_DEBUG, "Blank %d x %d\n",
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hblank, vblank);
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printk(BIOS_DEBUG, "Sync %d x %d\n",
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hsync, vsync);
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printk(BIOS_DEBUG, "Front porch %d x %d\n",
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hfront_porch, vfront_porch);
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printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock
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? "Spread spectrum clock\n" : "DREF clock\n"));
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printk(BIOS_DEBUG,
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mode->lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
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printk(BIOS_DEBUG, "Polarities %d, %d\n",
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hpolarity, vpolarity);
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printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n",
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pixel_n, pixel_m1, pixel_m2, pixel_p1);
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printk(BIOS_DEBUG, "Pixel clock %d kHz\n",
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BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) /
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(pixel_n + 2) / (pixel_p1 * pixel_p2));
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write32(mmio + LVDS,
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(hpolarity << 20) | (vpolarity << 21)
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| (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
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| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
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| LVDS_ENABLE_DITHER
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| LVDS_CLOCK_A_POWERUP_ALL
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| LVDS_PIPE(0));
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mdelay(1);
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write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS
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| (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK));
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write32(mmio + FP0(0),
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(pixel_n << 16)
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| (pixel_m1 << 8) | (pixel_m2));
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write32(mmio + DPLL(0),
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DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
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| DPLL_VGA_MODE_DIS
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| (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
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: DPLLB_LVDS_P2_CLOCK_DIV_14)
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| (0x10000 << (pixel_p1 - 1))
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| ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
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| (6 << PLL_LOAD_PULSE_PHASE_SHIFT));
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mdelay(1);
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write32(mmio + DPLL(0),
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DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
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| DPLL_VGA_MODE_DIS
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| (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
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: DPLLB_LVDS_P2_CLOCK_DIV_14)
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| (0x10000 << (pixel_p1 - 1))
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| ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
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| (6 << PLL_LOAD_PULSE_PHASE_SHIFT));
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/* Re-lock the registers. */
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write32(mmio + PP_CONTROL,
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(read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK));
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write32(mmio + LVDS,
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(hpolarity << 20) | (vpolarity << 21)
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| (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
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| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
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| LVDS_CLOCK_A_POWERUP_ALL
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| LVDS_ENABLE_DITHER
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| LVDS_PIPE(0));
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write32(mmio + HTOTAL(0),
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((hactive + right_border + hblank - 1) << 16)
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| (hactive - 1));
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write32(mmio + HBLANK(0),
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((hactive + right_border + hblank - 1) << 16)
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| (hactive + right_border - 1));
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write32(mmio + HSYNC(0),
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((hactive + right_border + hfront_porch + hsync - 1) << 16)
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| (hactive + right_border + hfront_porch - 1));
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write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16)
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| (vactive - 1));
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write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16)
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| (vactive + bottom_border - 1));
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write32(mmio + VSYNC(0),
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((vactive + bottom_border + vfront_porch + vsync - 1) << 16)
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| (vactive + bottom_border + vfront_porch - 1));
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write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
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write32(mmio + PF_WIN_POS(0), 0);
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if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
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write32(mmio + PIPESRC(0), ((hactive - 1) << 16)
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| (vactive - 1));
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write32(mmio + PF_CTL(0), 0);
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write32(mmio + PF_WIN_SZ(0), 0);
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write32(mmio + PFIT_CONTROL, 0);
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} else {
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write32(mmio + PIPESRC(0), (639 << 16) | 399);
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write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3);
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write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
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write32(mmio + PFIT_CONTROL, 0x80000000);
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}
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mdelay(1);
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write32(mmio + PIPECONF(0), PIPECONF_BPP_6);
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write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
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write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
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if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
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write32(mmio + VGACNTRL, VGA_DISP_DISABLE);
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write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE
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| DISPPLANE_BGRX888);
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mdelay(1);
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} else {
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write32(mmio + VGACNTRL, 0xc4008e);
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}
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write32(mmio + LVDS, LVDS_PORT_ENABLE
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| (hpolarity << 20) | (vpolarity << 21)
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| (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
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| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
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| LVDS_CLOCK_A_POWERUP_ALL
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| LVDS_ENABLE_DITHER
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| LVDS_PIPE(0));
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write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
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/* Enable screen memory. */
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vga_sr_write(1, vga_sr_read(1) & ~0x20);
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/* Clear interrupts. */
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write32(mmio + DEIIR, 0xffffffff);
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write32(mmio + SDEIIR, 0xffffffff);
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if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
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memset((void *) lfb, 0,
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edid->x_resolution * edid->y_resolution * 4);
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set_vbe_mode_info_valid(edid, lfb);
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}
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}
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static void gma_init_vga(const struct northbridge_intel_gm45_config *info,
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u8 *mmio, u32 physbase, u16 piobase, u32 lfb,
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struct edid *edid)
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{
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int i;
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struct edid_mode *mode;
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u32 hactive, vactive, right_border, bottom_border;
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int hpolarity, vpolarity;
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u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch;
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u32 target_frequency;
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u32 smallest_err = 0xffffffff;
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u32 pixel_p1 = 1;
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u32 pixel_p2;
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u32 pixel_n = 1;
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u32 pixel_m1 = 1;
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u32 pixel_m2 = 1;
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vga_gr_write(0x18, 0);
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/* Set up GTT. */
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for (i = 0; i < 0x2000; i++) {
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outl((i << 2) | 1, piobase);
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outl(physbase + (i << 12) + 1, piobase + 4);
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}
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write32(mmio + VGA0, 0x31108);
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write32(mmio + VGA1, 0x31406);
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write32(mmio + ADPA, ADPA_DAC_ENABLE
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| ADPA_PIPE_A_SELECT
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| ADPA_CRT_HOTPLUG_MONITOR_COLOR
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| ADPA_CRT_HOTPLUG_ENABLE
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| ADPA_USE_VGA_HVPOLARITY
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| ADPA_VSYNC_CNTL_ENABLE
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| ADPA_HSYNC_CNTL_ENABLE
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| ADPA_DPMS_ON);
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write32(mmio + 0x7041c, 0x0);
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write32(mmio + DPLL_MD(0), 0x3);
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write32(mmio + DPLL_MD(1), 0x3);
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vga_misc_write(0x67);
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const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
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0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
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0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,
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0xff
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};
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vga_cr_write(0x11, 0);
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for (i = 0; i <= 0x18; i++)
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vga_cr_write(i, cr[i]);
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udelay(1);
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/* Disable screen memory to prevent garbage from appearing. */
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vga_sr_write(1, vga_sr_read(1) | 0x20);
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mode = &edid->mode;
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hactive = edid->x_resolution;
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vactive = edid->y_resolution;
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right_border = mode->hborder;
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bottom_border = mode->vborder;
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hpolarity = (mode->phsync == '-');
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vpolarity = (mode->pvsync == '-');
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vsync = mode->vspw;
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hsync = mode->hspw;
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vblank = mode->vbl;
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hblank = mode->hbl;
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hfront_porch = mode->hso;
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vfront_porch = mode->vso;
|
||||
target_frequency = mode->pixel_clock;
|
||||
|
||||
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
|
||||
vga_sr_write(1, 1);
|
||||
vga_sr_write(0x2, 0xf);
|
||||
vga_sr_write(0x3, 0x0);
|
||||
vga_sr_write(0x4, 0xe);
|
||||
vga_gr_write(0, 0x0);
|
||||
vga_gr_write(1, 0x0);
|
||||
vga_gr_write(2, 0x0);
|
||||
vga_gr_write(3, 0x0);
|
||||
vga_gr_write(4, 0x0);
|
||||
vga_gr_write(5, 0x0);
|
||||
vga_gr_write(6, 0x5);
|
||||
vga_gr_write(7, 0xf);
|
||||
vga_gr_write(0x10, 0x1);
|
||||
vga_gr_write(0x11, 0);
|
||||
|
||||
edid->bytes_per_line = (edid->bytes_per_line + 63) & ~63;
|
||||
|
||||
write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE
|
||||
| DISPPLANE_BGRX888);
|
||||
write32(mmio + DSPADDR(0), 0);
|
||||
write32(mmio + DSPSTRIDE(0), edid->bytes_per_line);
|
||||
write32(mmio + DSPSURF(0), 0);
|
||||
for (i = 0; i < 0x100; i++)
|
||||
write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
|
||||
} else {
|
||||
vga_textmode_init();
|
||||
}
|
||||
|
||||
pixel_p2 = target_frequency <= 225000 ? 10 : 5;
|
||||
|
||||
u32 candn, candm1, candm2, candp1;
|
||||
for (candn = 1; candn <= 4; candn++) {
|
||||
for (candm1 = 23; candm1 >= 17; candm1--) {
|
||||
for (candm2 = 11; candm2 >= 5; candm2--) {
|
||||
for (candp1 = 8; candp1 >= 1; candp1--) {
|
||||
u32 m = 5 * (candm1 + 2) + (candm2 + 2);
|
||||
u32 p = candp1 * pixel_p2;
|
||||
u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2);
|
||||
u32 dot = DIV_ROUND_CLOSEST(vco, p);
|
||||
u32 this_err = MAX(dot, target_frequency) -
|
||||
MIN(dot, target_frequency);
|
||||
if (this_err < smallest_err) {
|
||||
smallest_err= this_err;
|
||||
pixel_n = candn;
|
||||
pixel_m1 = candm1;
|
||||
pixel_m2 = candm2;
|
||||
pixel_p1 = candp1;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (smallest_err == 0xffffffff) {
|
||||
printk(BIOS_ERR, "Error: Couldn't find GFX clock divisors\n");
|
||||
return;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "Bringing up panel at resolution %d x %d\n",
|
||||
hactive, vactive);
|
||||
printk(BIOS_SPEW, "Borders %d x %d\n",
|
||||
right_border, bottom_border);
|
||||
printk(BIOS_SPEW, "Blank %d x %d\n",
|
||||
hblank, vblank);
|
||||
printk(BIOS_SPEW, "Sync %d x %d\n",
|
||||
hsync, vsync);
|
||||
printk(BIOS_SPEW, "Front porch %d x %d\n",
|
||||
hfront_porch, vfront_porch);
|
||||
printk(BIOS_SPEW, (info->gfx.use_spread_spectrum_clock
|
||||
? "Spread spectrum clock\n" : "DREF clock\n"));
|
||||
printk(BIOS_SPEW, "Polarities %d, %d\n",
|
||||
hpolarity, vpolarity);
|
||||
printk(BIOS_SPEW, "Pixel N=%d, M1=%d, M2=%d, P1=%d, P2=%d\n",
|
||||
pixel_n, pixel_m1, pixel_m2, pixel_p1, pixel_p2);
|
||||
printk(BIOS_SPEW, "Pixel clock %d kHz\n",
|
||||
BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) /
|
||||
(pixel_n + 2) / (pixel_p1 * pixel_p2));
|
||||
|
||||
mdelay(1);
|
||||
write32(mmio + FP0(0), (pixel_n << 16)
|
||||
| (pixel_m1 << 8) | pixel_m2);
|
||||
write32(mmio + DPLL(0), DPLL_VCO_ENABLE
|
||||
| DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL
|
||||
| (pixel_p2 == 10 ? DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 :
|
||||
DPLL_DAC_SERIAL_P2_CLOCK_DIV_5)
|
||||
| (0x10000 << (pixel_p1 - 1))
|
||||
| (6 << 9));
|
||||
|
||||
mdelay(1);
|
||||
write32(mmio + DPLL(0), DPLL_VCO_ENABLE
|
||||
| DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL
|
||||
| (pixel_p2 == 10 ? DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 :
|
||||
DPLL_DAC_SERIAL_P2_CLOCK_DIV_5)
|
||||
| (0x10000 << (pixel_p1 - 1))
|
||||
| (6 << 9));
|
||||
|
||||
write32(mmio + ADPA, ADPA_DAC_ENABLE
|
||||
| ADPA_PIPE_A_SELECT
|
||||
| ADPA_CRT_HOTPLUG_MONITOR_COLOR
|
||||
| ADPA_CRT_HOTPLUG_ENABLE
|
||||
| ADPA_VSYNC_CNTL_ENABLE
|
||||
| ADPA_HSYNC_CNTL_ENABLE
|
||||
| ADPA_DPMS_ON
|
||||
| (vpolarity ? ADPA_VSYNC_ACTIVE_LOW :
|
||||
ADPA_VSYNC_ACTIVE_HIGH)
|
||||
| (hpolarity ? ADPA_HSYNC_ACTIVE_LOW :
|
||||
ADPA_HSYNC_ACTIVE_HIGH));
|
||||
|
||||
write32(mmio + HTOTAL(0),
|
||||
((hactive + right_border + hblank - 1) << 16)
|
||||
| (hactive - 1));
|
||||
write32(mmio + HBLANK(0),
|
||||
((hactive + right_border + hblank - 1) << 16)
|
||||
| (hactive + right_border - 1));
|
||||
write32(mmio + HSYNC(0),
|
||||
((hactive + right_border + hfront_porch + hsync - 1) << 16)
|
||||
| (hactive + right_border + hfront_porch - 1));
|
||||
|
||||
write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16)
|
||||
| (vactive - 1));
|
||||
write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16)
|
||||
| (vactive + bottom_border - 1));
|
||||
write32(mmio + VSYNC(0),
|
||||
((vactive + bottom_border + vfront_porch + vsync - 1) << 16)
|
||||
| (vactive + bottom_border + vfront_porch - 1));
|
||||
|
||||
write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
|
||||
|
||||
write32(mmio + PF_WIN_POS(0), 0);
|
||||
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
|
||||
write32(mmio + PIPESRC(0), ((hactive - 1) << 16)
|
||||
| (vactive - 1));
|
||||
write32(mmio + PF_CTL(0), 0);
|
||||
write32(mmio + PF_WIN_SZ(0), 0);
|
||||
write32(mmio + PFIT_CONTROL, 0);
|
||||
} else {
|
||||
write32(mmio + PIPESRC(0), (639 << 16) | 399);
|
||||
write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3);
|
||||
write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
|
||||
write32(mmio + PFIT_CONTROL, 0x80000000);
|
||||
}
|
||||
|
||||
mdelay(1);
|
||||
write32(mmio + PIPECONF(0), PIPECONF_BPP_6);
|
||||
write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
|
||||
write32(mmio + PIPECONF(0), PIPECONF_ENABLE
|
||||
| PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
|
||||
|
||||
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
|
||||
write32(mmio + VGACNTRL, VGA_DISP_DISABLE);
|
||||
write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE
|
||||
| DISPPLANE_BGRX888);
|
||||
mdelay(1);
|
||||
} else {
|
||||
write32(mmio + VGACNTRL, 0xc4008e);
|
||||
}
|
||||
|
||||
write32(mmio + ADPA, ADPA_DAC_ENABLE
|
||||
| ADPA_PIPE_A_SELECT
|
||||
| ADPA_CRT_HOTPLUG_MONITOR_COLOR
|
||||
| ADPA_CRT_HOTPLUG_ENABLE
|
||||
| ADPA_VSYNC_CNTL_ENABLE
|
||||
| ADPA_HSYNC_CNTL_ENABLE
|
||||
| ADPA_DPMS_ON
|
||||
| (vpolarity ? ADPA_VSYNC_ACTIVE_LOW :
|
||||
ADPA_VSYNC_ACTIVE_HIGH)
|
||||
| (hpolarity ? ADPA_HSYNC_ACTIVE_LOW :
|
||||
ADPA_HSYNC_ACTIVE_HIGH));
|
||||
|
||||
write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
|
||||
|
||||
/* Enable screen memory. */
|
||||
vga_sr_write(1, vga_sr_read(1) & ~0x20);
|
||||
|
||||
/* Clear interrupts. */
|
||||
write32(mmio + DEIIR, 0xffffffff);
|
||||
write32(mmio + SDEIIR, 0xffffffff);
|
||||
|
||||
if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
|
||||
memset((void *) lfb, 0,
|
||||
edid->x_resolution * edid->y_resolution * 4);
|
||||
set_vbe_mode_info_valid(edid, lfb);
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
static void gma_ngi(struct device *const dev, struct edid *edid_lvds)
|
||||
{
|
||||
u8 edid_data_vga[128];
|
||||
struct edid edid_vga;
|
||||
int vga_edid_status;
|
||||
u8 *mmio;
|
||||
struct northbridge_intel_gm45_config *conf = dev->chip_info;
|
||||
|
||||
mmio = res2mmio(gtt_res, 0, 0);
|
||||
printk(BIOS_DEBUG, "VGA EDID\n");
|
||||
intel_gmbus_read_edid(mmio + GMBUS0, GMBUS_PORT_VGADDC, 0x50,
|
||||
edid_data_vga, sizeof(edid_data_vga));
|
||||
intel_gmbus_stop(mmio + GMBUS0);
|
||||
vga_edid_status = decode_edid(edid_data_vga,
|
||||
sizeof(edid_data_vga), &edid_vga);
|
||||
|
||||
u32 physbase;
|
||||
struct resource *lfb_res;
|
||||
struct resource *pio_res;
|
||||
|
||||
lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2);
|
||||
pio_res = find_resource(dev, PCI_BASE_ADDRESS_4);
|
||||
|
||||
physbase = pci_read_config32(dev, 0x5c) & ~0xf;
|
||||
|
||||
if (!(physbase && pio_res && pio_res->base && lfb_res && lfb_res->base))
|
||||
return;
|
||||
|
||||
printk(BIOS_SPEW, "Initializing display without OPROM. MMIO 0x%llx\n",
|
||||
gtt_res->base);
|
||||
if (vga_edid_status != EDID_ABSENT) {
|
||||
printk(BIOS_DEBUG, "Initialising display on VGA output\n");
|
||||
gma_init_vga(conf, mmio, physbase, pio_res->base, lfb_res->base,
|
||||
&edid_vga);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "Initialising display on LVDS output\n");
|
||||
gma_init_lvds(conf, mmio, physbase, pio_res->base,
|
||||
lfb_res->base, edid_lvds);
|
||||
}
|
||||
|
||||
/* Linux relies on VBT for panel info. */
|
||||
generate_fake_intel_oprom(&conf->gfx, dev, "$VBT CANTIGA");
|
||||
}
|
||||
|
||||
static u32 get_cdclk(struct device *const dev)
|
||||
{
|
||||
const u16 cdclk_sel =
|
||||
|
|
@ -756,6 +177,7 @@ static void gma_func0_init(struct device *dev)
|
|||
u8 *mmio;
|
||||
u8 edid_data_lvds[128];
|
||||
struct edid edid_lvds;
|
||||
const struct northbridge_intel_gm45_config *const conf = dev->chip_info;
|
||||
|
||||
/* IGD needs to be Bus Master */
|
||||
reg32 = pci_read_config32(dev, PCI_COMMAND);
|
||||
|
|
@ -767,7 +189,8 @@ static void gma_func0_init(struct device *dev)
|
|||
return;
|
||||
mmio = res2mmio(gtt_res, 0, 0);
|
||||
|
||||
if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) {
|
||||
|
||||
if (!IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) {
|
||||
/* PCI Init, will run VBIOS */
|
||||
printk(BIOS_DEBUG, "Initialising IGD using VBIOS\n");
|
||||
pci_dev_init(dev);
|
||||
|
|
@ -782,17 +205,16 @@ static void gma_func0_init(struct device *dev)
|
|||
/* Post VBIOS init */
|
||||
gma_pm_init_post_vbios(dev, edid_lvds.ascii_string);
|
||||
|
||||
int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1;
|
||||
|
||||
if (vga_disable) {
|
||||
printk(BIOS_INFO,
|
||||
"IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n");
|
||||
} else {
|
||||
if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) {
|
||||
gma_ngi(dev, &edid_lvds);
|
||||
} else if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) {
|
||||
if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) {
|
||||
int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1;
|
||||
if (vga_disable) {
|
||||
printk(BIOS_INFO,
|
||||
"IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n");
|
||||
} else {
|
||||
int lightup_ok;
|
||||
gma_gfxinit(&lightup_ok);
|
||||
/* Linux relies on VBT for panel info. */
|
||||
generate_fake_intel_oprom(&conf->gfx, dev, "$VBT CANTIGA");
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue