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soc/intel/alderlake: Enable eMMC based on dev enabled 

1. Add eMMC device function in pci_devs.h.
2. Enable eMMC device and configuration based on dev enabled.
3. Add SOC acpi name for eMMC.

Change-Id: I44f17420f7a2a1ca0fbb6cfb1886b1617c5a5064
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Krishna Prasad Bhat 2022-01-16 23:16:24 +05:30 committed by Felix Held
parent d2ca5be61a
commit a6d642fa8d
4 changed files with 28 additions and 0 deletions
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3
src/soc/intel/alderlake/chip.c
View File

@ -110,6 +110,9 @@ const char *soc_acpi_name(const struct device *dev)
case PCH_DEVFN_HDA: return "HDAS"; case PCH_DEVFN_HDA: return "HDAS";
case PCH_DEVFN_SMBUS: return "SBUS"; case PCH_DEVFN_SMBUS: return "SBUS";
case PCH_DEVFN_GBE: return "GLAN"; case PCH_DEVFN_GBE: return "GLAN";
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
case PCH_DEVFN_EMMC: return "EMMC";
#endif
} }
return NULL; return NULL;

5
src/soc/intel/alderlake/chip.h
View File

@ -419,6 +419,11 @@ struct soc_intel_alderlake_config {
* accordingly */ * accordingly */
uint8_t HybridStorageMode; uint8_t HybridStorageMode;
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
/* eMMC HS400 mode */
uint8_t emmc_enable_hs400_mode;
#endif
/* /*
* Override CPU flex ratio value: * Override CPU flex ratio value:
* CPU ratio value controls the maximum processor non-turbo ratio. * CPU ratio value controls the maximum processor non-turbo ratio.

14
src/soc/intel/alderlake/fsp_params.c
View File

@ -183,6 +183,14 @@ static const struct slot_irq_constraints irq_constraints[] = {
DIRECT_IRQ(PCH_DEVFN_UART2), DIRECT_IRQ(PCH_DEVFN_UART2),
}, },
}, },
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
{
.slot = PCH_DEV_SLOT_EMMC,
.fns = {
ANY_PIRQ(PCH_DEVFN_EMMC),
},
},
#endif
{ {
.slot = PCH_DEV_SLOT_PCIE, .slot = PCH_DEV_SLOT_PCIE,
.fns = { .fns = {
@ -596,6 +604,12 @@ static void fill_fsps_pm_timer_params(FSP_S_CONFIG *s_cfg,
static void fill_fsps_storage_params(FSP_S_CONFIG *s_cfg, static void fill_fsps_storage_params(FSP_S_CONFIG *s_cfg,
const struct soc_intel_alderlake_config *config) const struct soc_intel_alderlake_config *config)
{ {
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
/* eMMC Configuration */
s_cfg->ScsEmmcEnabled = is_devfn_enabled(PCH_DEVFN_EMMC);
if (s_cfg->ScsEmmcEnabled)
s_cfg->ScsEmmcHs400Enabled = config->emmc_enable_hs400_mode;
#endif
/* Enable Hybrid storage auto detection */ /* Enable Hybrid storage auto detection */
s_cfg->HybridStorageMode = config->HybridStorageMode; s_cfg->HybridStorageMode = config->HybridStorageMode;
} }

6
src/soc/intel/alderlake/include/soc/pci_devs.h
View File

@ -166,6 +166,12 @@
#define PCH_DEV_I2C5 _PCH_DEV(SIO4, 1) #define PCH_DEV_I2C5 _PCH_DEV(SIO4, 1)
#define PCH_DEV_UART2 _PCH_DEV(SIO4, 2) #define PCH_DEV_UART2 _PCH_DEV(SIO4, 2)
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
#define PCH_DEV_SLOT_EMMC 0x1a
#define PCH_DEVFN_EMMC _PCH_DEVFN(EMMC, 0)
#define PCH_DEV_EMMC _PCH_DEV(EMMC, 0)
#endif
#define PCH_DEV_SLOT_PCIE 0x1c #define PCH_DEV_SLOT_PCIE 0x1c
#define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0) #define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0)
#define PCH_DEVFN_PCIE2 _PCH_DEVFN(PCIE, 1) #define PCH_DEVFN_PCIE2 _PCH_DEVFN(PCIE, 1)