Fine-tune the V-link bus between K8T890 and VT8237R and set
it to 8X transfer rate (up to 1066 MB/s) similar code placed here would be needed for VT8237A/S etc. Using VIA recommended values despite they are for K8T890CF, this is K8T890CE (still dont know what is exactly different). This patch enables the parity error reporting on V-Link, so it enables NMI generation for the SERR# errors. The NMI may not be generated, maybe port 61h needs some tuning too. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2958 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Rudolf Marek
Uwe Hermann
parent
a422c2d3c6
commit
a6ddf253ad
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@ -23,3 +23,4 @@ driver k8t890_host.o
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driver k8t890_host_ctrl.o
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driver k8t890_pcie.o
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driver k8t890_traf_ctrl.o
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driver k8t890_error.o
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@ -23,6 +23,56 @@
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#include <device/pci_ids.h>
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#include <console/console.h>
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/**
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* Setup the V-Link for VT8237R, 8X mode.
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*
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* For K8T890CF VIA recommends what is in VIA column, AW is award 8X:
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*
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* REG DEF AW VIA-8X VIA-4X
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* -----------------------------
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* NB V-Link Manual Driving Control strobe 0xb5 0x46 0x46 0x88 0x88
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* NB V-Link Manual Driving Control - Data 0xb6 0x46 0x46 0x88 0x88
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* NB V-Link Receiving Strobe Delay 0xb7 0x02 0x02 0x61 0x01
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* NB V-Link Compensation Control bit4,0 (b5,b6) 0xb4 0x10 0x10 0x11 0x11
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* SB V-Link Strobe Drive Control 0xb9 0x00 0xa5 0x98 0x98
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* SB V-Link Data drive Control???? 0xba 0x00 0xbb 0x77 0x77
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* SB V-Link Receive Strobe Delay???? 0xbb 0x04 0x11 0x11 0x11
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* SB V-Link Compensation Control bit0 (use b9) 0xb8 0x00 0x01 0x01 0x01
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* V-Link CKG Control 0xb0 0x05 0x05 0x06 0x03
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* V-Link CKG Control 0xb1 0x05 0x05 0x01 0x03
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*/
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static void ctrl_init(struct device *dev)
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{
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u8 reg;
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device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA,
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PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
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if (!devsb)
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return;
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pci_write_config8(dev, 0xb5, 0x88);
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pci_write_config8(dev, 0xb6, 0x88);
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pci_write_config8(dev, 0xb7, 0x61);
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reg = pci_read_config8(dev, 0xb4);
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reg |= 0x11;
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pci_write_config8(dev, 0xb4, reg);
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pci_write_config8(dev, 0xb9, 0x98);
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pci_write_config8(dev, 0xba, 0x77);
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pci_write_config8(dev, 0xbb, 0x11);
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reg = pci_read_config8(dev, 0xb8);
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reg |= 0x1;
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pci_write_config8(dev, 0xb8, reg);
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pci_write_config8(dev, 0xb0, 0x06);
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pci_write_config8(dev, 0xb1, 0x01);
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/* Program V-link 8X 16bit full duplex, parity enabled. */
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pci_write_config8(dev, 0x48, 0xa3);
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}
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static void ctrl_enable(struct device *dev)
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{
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u8 regm, regm2, regm3;
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@ -36,11 +86,6 @@ static void ctrl_enable(struct device *dev)
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/* PCI CFG Address bits[27:24] are used as extended register address
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bit[11:8] */
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pci_write_config8(dev, 0x47, 0x30);
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/* FIXME: Program V-link 8X 16bit full duplex, this needs to be fixed
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for other than VT8237R SB */
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pci_write_config8(dev, 0x48, 0x23);
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/* Magic init. This is not well documented :/ */
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pci_write_config8(dev, 0x70, 0xc2);
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@ -92,6 +137,7 @@ static struct device_operations ctrl_ops = {
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.enable = ctrl_enable,
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.init = ctrl_init,
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.ops_pci = 0,
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};
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@ -0,0 +1,47 @@
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/*
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License v2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <console/console.h>
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static void error_enable(struct device *dev)
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{
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/*
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* bit0 - Enable V-link parity error reporting in 0x50 bit0 (RWC)
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* bit6 - Parity Error/SERR# Report Through V-Link to SB
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* bit7 - Parity Error/SERR# Report Through NMI
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*/
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pci_write_config8(dev, 0x58, 0x81);
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}
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static const struct device_operations error_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.enable = error_enable,
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.ops_pci = 0,
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};
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static const struct pci_driver northbridge_driver __pci_driver = {
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.ops = &error_ops,
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.vendor = PCI_VENDOR_ID_VIA,
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.device = PCI_DEVICE_ID_VIA_K8T890CE_1,
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};
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