From a6fe456cb52c5133eb5e09d11dc83c0419b5692a Mon Sep 17 00:00:00 2001 From: Tristan Corrick Date: Wed, 26 Dec 2018 23:46:27 +1300 Subject: [PATCH] Doc/nb/intel/haswell: Add a list of known issues Change-Id: If0339831550f6c70e8056f78633e9a402f35a793 Signed-off-by: Tristan Corrick Reviewed-on: https://review.coreboot.org/c/30455 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- Documentation/mainboard/asrock/h81m-hds.md | 4 +++ .../northbridge/intel/haswell/index.md | 4 +++ .../northbridge/intel/haswell/known-issues.md | 28 +++++++++++++++++++ 3 files changed, 36 insertions(+) create mode 100644 Documentation/northbridge/intel/haswell/known-issues.md diff --git a/Documentation/mainboard/asrock/h81m-hds.md b/Documentation/mainboard/asrock/h81m-hds.md index 460af8feaf..5e80f2b92c 100644 --- a/Documentation/mainboard/asrock/h81m-hds.md +++ b/Documentation/mainboard/asrock/h81m-hds.md @@ -78,6 +78,10 @@ facing towards the bottom of the board. in coreboot. The `coretemp` driver can still be used for accurate CPU temperature readings from an OS. +```eval_rst +Please also see :doc:`../../northbridge/intel/haswell/known-issues`. +``` + ## Untested - parallel port diff --git a/Documentation/northbridge/intel/haswell/index.md b/Documentation/northbridge/intel/haswell/index.md index 3eb80594b8..87fb56f483 100644 --- a/Documentation/northbridge/intel/haswell/index.md +++ b/Documentation/northbridge/intel/haswell/index.md @@ -6,3 +6,7 @@ coreboot. ## Proprietary blobs - [mrc.bin](mrc.bin.md) + +## Issues + +- [Known issues](known-issues.md) diff --git a/Documentation/northbridge/intel/haswell/known-issues.md b/Documentation/northbridge/intel/haswell/known-issues.md new file mode 100644 index 0000000000..c684b8fd65 --- /dev/null +++ b/Documentation/northbridge/intel/haswell/known-issues.md @@ -0,0 +1,28 @@ +# Known issues with Haswell + +These issues are specific to the Haswell architecture. For a given +mainboard, there might be additional issues to those listed here. + +## PCIe graphics + +```eval_rst +Using a PCIe graphics card for display output is not currently +supported. This is because :doc:`./mrc.bin` requires workarounds to +have such a feature working correctly. +``` + +However, there is a [patch on Gerrit][hsw-gfx-gerrit] that allows PCIe +graphics to be used for display output. This patch is not guaranteed to +be of the same level of quality as code committed to coreboot. + +Still, in some cases, a PCIe graphics card can be used for rendering, +while the integrated graphics device is used for display output. This +can be achieved under GNU/Linux by using [PRIME GPU offloading][PRIME]. + +## PCIe 3.0 + +Only PCIe 2.0 has been tested so far. PCIe 3.0 could potentially have +stability issues. + +[PRIME]: https://wiki.archlinux.org/index.php/PRIME +[hsw-gfx-gerrit]: https://review.coreboot.org/c/30456