First SPD code in and working!
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1177 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
cb3f498296
commit
a70483b83b
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@ -34,23 +34,23 @@ static void memreset_setup(void)
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}
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/*
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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}
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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}
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*/
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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unsigned char c;
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c = smbus_read_byte(device, address);
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return c;
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unsigned char c;
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c = smbus_read_byte(device, address);
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return c;
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}
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#include "northbridge/via/vt8601/raminit.c"
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/*
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#include "sdram/generic_sdram.c"
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*/
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#include "sdram/generic_sdram.c"
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*/
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static void
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enable_mainboard_devices(void) {
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@ -96,47 +96,40 @@ static void main(void)
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/* init_timer();*/
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outb(5, 0x80);
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enable_vt8231_serial();
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enable_mainboard_devices();
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uart_init();
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console_init();
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enable_vt8231_serial();
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enable_mainboard_devices();
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uart_init();
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console_init();
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enable_smbus();
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enable_shadow_ram();
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/*
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memreset_setup();
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this is way more generic than we need.
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sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
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*/
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sdram_set_registers((const struct mem_controller *) 0);
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enable_smbus();
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enable_shadow_ram();
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/*
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memreset_setup();
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this is way more generic than we need.
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sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
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*/
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sdram_set_registers((const struct mem_controller *) 0);
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sdram_set_spd_registers((const struct mem_controller *) 0);
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sdram_enable(0, (const struct mem_controller *) 0);
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/* Check all of memory */
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/* Check all of memory */
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#if 0
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msr_t msr;
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msr = rdmsr(TOP_MEM);
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print_debug("TOP_MEM: ");
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print_debug_hex32(msr.hi);
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print_debug_hex32(msr.lo);
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print_debug("\r\n");
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ram_check(0x00000000, msr.lo);
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#endif
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#if 0
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ram_check(0x00000000, msr.lo);
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#endif
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#if 0
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static const struct {
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unsigned long lo, hi;
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} check_addrs[] = {
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/* Check 16MB of memory @ 0*/
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{ 0x00000000, 0x01000000 },
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static const struct {
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unsigned long lo, hi;
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} check_addrs[] = {
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/* Check 16MB of memory @ 0*/
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{ 0x00000000, 0x01000000 },
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#if TOTAL_CPUS > 1
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/* Check 16MB of memory @ 2GB */
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{ 0x80000000, 0x81000000 },
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/* Check 16MB of memory @ 2GB */
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{ 0x80000000, 0x81000000 },
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#endif
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};
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int i;
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for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
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ram_check(check_addrs[i].lo, check_addrs[i].hi);
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}
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};
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int i;
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for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
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ram_check(check_addrs[i].lo, check_addrs[i].hi);
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}
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#endif
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}
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@ -13,12 +13,16 @@
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#include "chip.h"
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#include "northbridge.h"
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static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
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0x56, 0x57};
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struct mem_range *sizeram(void)
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{
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unsigned long mmio_basek;
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static struct mem_range mem[10];
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device_t dev;
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int i, idx;
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unsigned char rambits;
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dev = dev_find_slot(0, 0);
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if (!dev) {
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@ -33,7 +37,24 @@ struct mem_range *sizeram(void)
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mem[idx].sizek = 0;
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idx++;
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}
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for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) {
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unsigned char reg;
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reg = pci_read_config8(dev, ramregs[i]);
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/* these are ENDING addresses, not sizes.
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* if there is memory in this slot, then reg will be > rambits.
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* So we just take the max, that gives us total.
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* We take the highest one to cover for once and future linuxbios
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* bugs. We warn about bugs.
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*/
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if (reg > rambits)
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rambits = reg;
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if (reg < rambits)
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printk_err("ERROR! register 0x%x is not set!\n",
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ramregs[i]);
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}
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printk_err("I would set ram size to 0x%x Mbytes\n", (1 <<rambits)*8);
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#if 1
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for(i = 0; i < idx; i++) {
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printk_debug("mem[%d].basek = %08x mem[%d].sizek = %08x\n",
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@ -58,7 +79,7 @@ static void enumerate(struct chip *chip)
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*/
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static void
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random_fixup() {
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device_t *pcidev = dev_find_slot(0, 0);
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device_t pcidev = dev_find_slot(0, 0);
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printk_spew("VT8601 random fixup ...\n");
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if (pcidev) {
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@ -1,6 +1,6 @@
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#include <cpu/p6/mtrr.h>
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#include "raminit.h"
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#if 0
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/*
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This software and ancillary information (herein called SOFTWARE )
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called LinuxBIOS is made available under the terms described
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@ -32,278 +32,12 @@ it with the version available from LANL.
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* (Rest of configuration is done in C)
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* 5/19/03 by SONE Takeshi <ts1@tsn.or.jp>
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*/
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/* converted to C 9/2003 Ron Minnich */
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/* Stable ~1 usec delay by hitting unused ISA port. */
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#define UDELAY(x) movl $x,%ecx; 9: outb %al,$0x81; loop 9b
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#define DIMMS_READ(x) \
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movl 0x00000000+x, %eax; \
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movl 0x10000000+x, %eax; \
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movl 0x20000000+x, %eax; \
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movl 0x30000000+x, %eax; \
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movl 0x40000000+x, %eax; \
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movl 0x50000000+x, %eax
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#define DIMMS_WRITE(x) \
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movl %eax, 0x00000000+x; \
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movl %eax, 0x10000000+x; \
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movl %eax, 0x20000000+x; \
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movl %eax, 0x30000000+x; \
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movl %eax, 0x40000000+x; \
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movl %eax, 0x50000000+x
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raminit:
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intel_chip_post_macro(0x35)
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// memory clk enable. We are not using ECC
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CS_WRITE($0x78, $0x01)
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// dram control, see the book.
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#if DIMM_PC133
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CS_WRITE($0x68, $0x52)
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#else
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CS_WRITE($0x68, $0x42)
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#endif
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// dram control, see the book.
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CS_WRITE($0x6B, $0x0c)
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// Initial setting, 256MB in each bank, will be rewritten later.
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CS_WRITE($0x5A, $0x20)
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CS_WRITE($0x5B, $0x40)
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CS_WRITE($0x5C, $0x60)
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CS_WRITE($0x5D, $0x80)
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CS_WRITE($0x5E, $0xA0)
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CS_WRITE($0x5F, $0xC0)
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// It seems we have to take care of these 2 registers as if
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// they are bank 6 and 7.
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CS_WRITE($0x56, $0xC0)
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CS_WRITE($0x57, $0xC0)
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// SDRAM in all banks
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CS_WRITE($0x60, $0x3F)
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// DRAM timing. I'm suspicious of this
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// This is for all banks, 64 is 0,1. 65 is 2,3. 66 is 4,5.
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// ras precharge 4T, RAS pulse 5T
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// cas2 is 0xd6, cas3 is 0xe6
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// we're also backing off write pulse width to 2T, so result is 0xee
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#if DIMM_CL2
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CS_WRITE($0x64, $0xd4)
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CS_WRITE($0x65, $0xd4)
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CS_WRITE($0x66, $0xd4)
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#else // CL=3
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CS_WRITE($0x64, $0xe4)
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CS_WRITE($0x65, $0xe4)
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CS_WRITE($0x66, $0xe4)
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#endif
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// dram frequency select.
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// enable 4K pages for 64M dram.
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#if DIMM_PC133
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CS_WRITE($0x69, $0x3c)
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#else
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CS_WRITE($0x69, $0xac)
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#endif
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// refresh counter, disabled.
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CS_WRITE($0x6A, $0x00)
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// clkenable configuration. kevinh FIXME - add precharge
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CS_WRITE($0x6C, $0x00)
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// dram read latch delay of 1 ns, MD drive 8 mA,
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// high drive strength on MA[2: 13], we#, cas#, ras#
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// As per Cindy Lee, set to 0x37, not 0x57
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CS_WRITE($0x6D, $0x7f)
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/* Initialize all banks at once */
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/* begin to initialize*/
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// I forget why we need this, but we do
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mov $0xa55a5aa5, %eax
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DIMMS_WRITE(0)
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/* set NOP*/
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CS_WRITE($0x6C, $0x01)
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/* wait 200us*/
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// You need to do the memory reference. That causes the nop cycle.
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DIMMS_READ(0)
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UDELAY(400)
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/* set precharge */
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CS_WRITE($0x6C, $0x02)
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/* dummy reads*/
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DIMMS_READ(0)
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UDELAY(200)
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/* set CBR*/
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CS_WRITE($0x6C, $0x04)
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/* do 8 reads and wait >100us between each - from via*/
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DIMMS_READ(0)
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UDELAY(200)
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DIMMS_READ(0)
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UDELAY(200)
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DIMMS_READ(0)
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UDELAY(200)
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DIMMS_READ(0)
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UDELAY(200)
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DIMMS_READ(0)
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UDELAY(200)
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DIMMS_READ(0)
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UDELAY(200)
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DIMMS_READ(0)
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UDELAY(200)
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DIMMS_READ(0)
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UDELAY(200)
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/* set MRS*/
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CS_WRITE($0x6c, $0x03)
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#if DIMM_CL2
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DIMMS_READ(0x150)
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#else // CL=3
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DIMMS_READ(0x1d0)
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#endif
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UDELAY(200)
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/* set to normal mode */
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CS_WRITE($0x6C, $0x08)
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movl $0x55aa55aa, %eax
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DIMMS_WRITE(0)
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DIMMS_READ(0)
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UDELAY(200)
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// Set the refresh rate.
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#if DIMM_PC133
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CS_WRITE($0x6A, $0x86)
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#else
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CS_WRITE($0x6A, $0x65)
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#endif
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// enable multi-page open
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CS_WRITE($0x6B, $0x0d)
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/* Begin auto-detection
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* Find the first bank with DIMM equipped. */
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/* Maximum possible memory in bank 0, none in other banks.
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* Starting from bank 0, we's fill 0 in these registers
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* until memory is found. */
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CS_WRITE($0x5A, $0xff)
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CS_WRITE($0x5B, $0xff)
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CS_WRITE($0x5C, $0xff)
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CS_WRITE($0x5D, $0xff)
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CS_WRITE($0x5E, $0xff)
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CS_WRITE($0x5F, $0xff)
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CS_WRITE($0x56, $0xff)
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CS_WRITE($0x57, $0xff)
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movl $0x5A, %ebx // first bank
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1:
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/* Write different values to 0 and 8, then read from 0.
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* If values of address 0 match, we have something there. */
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movl $0x12345678, %eax
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movl %eax, 0
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movl $0x87654321, %edx
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movl %edx, 8
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movl 0, %edx
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cmpl %eax, %edx
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je 2f
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/* No memory in this bank. Tell it to the bridge. */
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movl %ebx, %eax
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xorl %edx, %edx
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PCI_WRITE_CONFIG_BYTE
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incl %ebx
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cmpl $0x60, %ebx
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jne 1b
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/* No memory at all! */
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CONSOLE_EMERG_TX_STRING($msg_nomem)
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1:
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hlt
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jmp 1b
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2:
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/* Detect MA mapping type of the first bank. */
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jmp raminit_ma
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raminit_ma_reg_table:
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/* Values for MA type register to try */
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.word 0x0000, 0x8088, 0xe0ee
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.word 0xffff // end mark
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raminit_ma:
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xorl %esi, %esi // highest address
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movl $raminit_ma_reg_table, %ebx
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1:
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movw (%ebx), %cx
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cmpw $0xffff, %cx
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je raminit_ma_done
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movl $0x58, %eax
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PCI_WRITE_CONFIG_WORD
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xorl %eax, %eax
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movl %eax, (%eax)
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// Write to addresses with only one address bit on,
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// from 0x80000000 to 0x00000008 (lower 3 bits are ignored, assuming
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// 64-bit bus).
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// Then what is read at address 0 is the value written to the lowest
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// address where it gets wrap-around. That address is either the size
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// of the bank, or a missing bit due to incorrect MA mapping.
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movl $0x80000000, %eax
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2:
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movl %eax, (%eax)
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shrl $1, %eax
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cmpl $4, %eax
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jne 2b
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movl 0, %eax
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cmpl %eax, %esi
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jnc 3f
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// This is the current best MA mapping.
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// Save the address and its MA mapping value.
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movl %eax, %esi
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movl %ecx, %edi
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3:
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incl %ebx
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incl %ebx
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jmp 1b
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raminit_ma_done:
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// Set the best (hopefully correct) MA mapping type.
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movl $0x58, %eax
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movl %edi, %ecx
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PCI_WRITE_CONFIG_WORD
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CONSOLE_DEBUG_TX_STRING($msg_enabled)
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CONSOLE_DEBUG_TX_HEX32(%esi)
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CONSOLE_DEBUG_TX_STRING($msg_bytes)
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/*
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* We have the size of first bank in %esi, but throwing it away.
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* Sizing will again be done in C, because we'll configure the rest
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* of banks in there anyway.
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*/
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//CALLSP(dumpnorth)
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intel_chip_post_macro(0x36)
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.section ".rom.data"
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msg_nomem:
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.asciz "No memory\r\n"
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msg_enabled:
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.asciz "Enabled first bank of RAM: 0x"
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msg_bytes:
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.asciz " bytes\r\n"
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.previous
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#endif
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/* this is an early hack. We're going to just try to get memory
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* working as it was before. I need help for SPD! RGM
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*/
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// Set to 1 if your DIMMs are PC133
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// Note that I'm assuming CPU's FSB frequency is 133MHz. If your CPU runs
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// at another bus speed, you might need to change some of register values.
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/* Set to 1 if your DIMMs are PC133 Note that I'm assuming CPU's FSB
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* frequency is 133MHz. If your CPU runs at another bus speed, you
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* might need to change some of register values.
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*/
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#ifndef DIMM_PC133
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#define DIMM_PC133 0
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#endif
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@ -313,19 +47,19 @@ msg_bytes:
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#define DIMM_CL2 0
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#endif
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void dimms_read(unsigned long x) {
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uint8_t c;
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unsigned long eax;
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volatile unsigned long y;
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eax = x;
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for(c = 0; c < 6; c++) {
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print_err("dimms_read: ");
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print_err_hex32(eax);
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print_err("\r\n");
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y = * (volatile unsigned long *) eax;
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eax += 0x10000000;
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}
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void dimms_read(unsigned long x) {
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uint8_t c;
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unsigned long eax;
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volatile unsigned long y;
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eax = x;
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for(c = 0; c < 6; c++) {
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||||
print_err("dimms_read: ");
|
||||
print_err_hex32(eax);
|
||||
print_err("\r\n");
|
||||
y = * (volatile unsigned long *) eax;
|
||||
eax += 0x10000000;
|
||||
}
|
||||
}
|
||||
|
||||
void dimms_write(int x) {
|
||||
|
|
@ -340,8 +74,9 @@ void dimms_write(int x) {
|
|||
}
|
||||
}
|
||||
|
||||
#define setnorthb pci_write_config8
|
||||
#if 0
|
||||
|
||||
|
||||
#ifdef DEBUG_SETNORTHB
|
||||
void setnorthb(device_t north, uint8_t reg, uint8_t val) {
|
||||
print_err("setnorth: reg ");
|
||||
print_err_hex8(reg);
|
||||
|
|
@ -350,6 +85,8 @@ void setnorthb(device_t north, uint8_t reg, uint8_t val) {
|
|||
print_err("\r\n");
|
||||
pci_write_config8(north, reg, val);
|
||||
}
|
||||
#else
|
||||
#define setnorthb pci_write_config8
|
||||
#endif
|
||||
|
||||
void
|
||||
|
|
@ -371,10 +108,10 @@ static void sdram_set_registers(const struct mem_controller *ctrl) {
|
|||
0x0000, 0x8088, 0xe0ee,
|
||||
0xffff // end mark
|
||||
};
|
||||
static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
|
||||
static const unsigned char ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
|
||||
0x56, 0x57};
|
||||
|
||||
device_t north = 0;
|
||||
device_t north = (device_t) 0;
|
||||
uint8_t c, r;
|
||||
|
||||
print_err("vt8601 init starting\n");
|
||||
|
|
@ -386,7 +123,10 @@ static void sdram_set_registers(const struct mem_controller *ctrl) {
|
|||
print_err(" ");
|
||||
print_err_hex16(pci_read_config16(north, 2));
|
||||
print_err("\r\n");
|
||||
|
||||
|
||||
/* All we are doing now is setting initial known-good values that will
|
||||
* be revised later as we read SPD
|
||||
*/
|
||||
// memory clk enable. We are not using ECC
|
||||
pci_write_config8(north,0x78, 0x01);
|
||||
print_err_hex8(pci_read_config8(north, 0x78));
|
||||
|
|
@ -435,8 +175,12 @@ static void sdram_set_registers(const struct mem_controller *ctrl) {
|
|||
#else
|
||||
pci_write_config8(north,0x69, 0xac);
|
||||
#endif
|
||||
|
||||
/* IMPORTANT -- disable refresh counter */
|
||||
// refresh counter, disabled.
|
||||
pci_write_config8(north,0x6A, 0x00);
|
||||
|
||||
|
||||
// clkenable configuration. kevinh FIXME - add precharge
|
||||
pci_write_config8(north,0x6C, 0x00);
|
||||
// dram read latch delay of 1 ns, MD drive 8 mA,
|
||||
|
|
@ -446,6 +190,75 @@ static void sdram_set_registers(const struct mem_controller *ctrl) {
|
|||
|
||||
/* Initialize all banks at once */
|
||||
|
||||
}
|
||||
|
||||
/* slot is the dram slot. Base is the *8M base. */
|
||||
static unsigned char
|
||||
do_module_size(unsigned char slot) { /*, unsigned char base) */
|
||||
static const unsigned char log2[256] = {[1] = 0, [2] = 1, [4] = 2, [8] = 3,
|
||||
[16]=4, [32]=5, [64]=6,
|
||||
[128]=7};
|
||||
static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
|
||||
0x56, 0x57};
|
||||
device_t north = 0;
|
||||
/* for all the DRAMS, see if they are there and get the size of each
|
||||
* module. This is just a very early first cut at sizing.
|
||||
*/
|
||||
/* we may run out of registers ... */
|
||||
unsigned char width, banks, rows, cols, reg;
|
||||
unsigned char value = 0;
|
||||
unsigned char module = 0xa1 | (slot << 1);
|
||||
/* is the module there? if byte 2 is not 4, then we'll assume it
|
||||
* is useless.
|
||||
*/
|
||||
if (smbus_read_byte(module, 2) != 4)
|
||||
goto done;
|
||||
|
||||
//print_err_hex8(slot);
|
||||
// print_err(" is SDRAM\n");
|
||||
width = smbus_read_byte(module, 6) | (smbus_read_byte(module,7)<<0);
|
||||
banks = smbus_read_byte(module, 17);
|
||||
/* we're going to assume symmetric banks. Sorry. */
|
||||
cols = smbus_read_byte(module, 4) & 0xf;
|
||||
rows = smbus_read_byte(module, 3) & 0xf;
|
||||
/* grand total. You have rows+cols addressing, * times of banks, times
|
||||
* width of data in bytes*/
|
||||
/* do this in terms of address bits. Then subtract 23 from it.
|
||||
* That might do it.
|
||||
*/
|
||||
value = cols + rows + log2[banks] + log2[width];
|
||||
value -= 23;
|
||||
/* now subtract 3 more bits as these are 8-bit bytes */
|
||||
value -= 3;
|
||||
// print_err_hex8(value);
|
||||
// print_err(" is the # bits for this bank\n");
|
||||
/* now put that size into the correct register */
|
||||
value = (1 << value);
|
||||
done:
|
||||
reg = ramregs[slot];
|
||||
|
||||
// print_err_hex8(value); print_err(" would go into ");
|
||||
// print_err_hex8(ramregs[reg]); print_err("\n");
|
||||
// pci_write_config8(north, ramregs[reg], value);
|
||||
return value;
|
||||
}
|
||||
|
||||
static void sdram_set_spd_registers(const struct mem_controller *ctrl) {
|
||||
|
||||
}
|
||||
|
||||
static void sdram_enable(int controllers, const struct mem_controller *ctrl) {
|
||||
unsigned char i;
|
||||
static const uint16_t raminit_ma_reg_table[] = {
|
||||
/* Values for MA type register to try */
|
||||
0x0000, 0x8088, 0xe0ee,
|
||||
0xffff // end mark
|
||||
};
|
||||
static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
|
||||
0x56, 0x57};
|
||||
|
||||
device_t north = 0;
|
||||
uint8_t c, r, base;
|
||||
/* begin to initialize*/
|
||||
// I forget why we need this, but we do
|
||||
dimms_write(0xa55a5aa5);
|
||||
|
|
@ -599,13 +412,37 @@ static void sdram_set_registers(const struct mem_controller *ctrl) {
|
|||
print_err("\r\n");
|
||||
}
|
||||
}
|
||||
base = 0;
|
||||
/* runs out of variable space. */
|
||||
/* this is unrolled and constants used as much as possible to help
|
||||
* us not run out of registers.
|
||||
* we'll run out of code space instead :-)
|
||||
*/
|
||||
// for(i = 0; i < 8; i++)
|
||||
base = do_module_size(0); /*, base);*/
|
||||
pci_write_config8(north, ramregs[0], base);
|
||||
base = do_module_size(1); /*, base);*/
|
||||
base += pci_read_config8(north, ramregs[0]);
|
||||
pci_write_config8(north, ramregs[1], base);
|
||||
/* runs out of code space. */
|
||||
for(i = 0; i < 8; i++){
|
||||
pci_write_config8(north, ramregs[i], base);
|
||||
/*
|
||||
pci_write_config8(north, ramregs[3], base);
|
||||
pci_write_config8(north, ramregs[4], base);
|
||||
pci_write_config8(north, ramregs[5], base);
|
||||
pci_write_config8(north, ramregs[6], base);
|
||||
pci_write_config8(north, ramregs[7], base);
|
||||
*/
|
||||
}
|
||||
/*
|
||||
base = do_module_size(0xa0, base);
|
||||
base = do_module_size(0xa0, base);
|
||||
base = do_module_size(0xa0, base);
|
||||
base = do_module_size(0xa0, base);
|
||||
base = do_module_size(0xa0, base);
|
||||
base = do_module_size(0xa0, base);*/
|
||||
print_err("vt8601 done\n");
|
||||
dumpnorth(north);
|
||||
udelay(1000);
|
||||
}
|
||||
|
||||
static void sdram_set_spd_registers(const struct mem_controller *ctrl) {
|
||||
}
|
||||
|
||||
static void sdram_enable(int controllers, const struct mem_controller *ctrl) {
|
||||
}
|
||||
|
|
|
|||
|
|
@ -41,10 +41,14 @@ static void enable_smbus(void)
|
|||
c |= 5;
|
||||
pci_write_config8(dev, 0xd2, c);
|
||||
|
||||
c = pci_read_config8(dev, 0x54);
|
||||
c &= ~0x80;
|
||||
pci_write_config8(dev, 0xd2, c);
|
||||
|
||||
/* make it work for I/O ...
|
||||
*/
|
||||
dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
|
||||
c = pci_read_config8(dev, 4);
|
||||
c |= 1;
|
||||
pci_write_config8(dev, 4, c);
|
||||
print_err_hex8(c);
|
||||
print_err(" is the comm register\n");
|
||||
|
||||
print_debug("SMBus controller enabled\r\n");
|
||||
}
|
||||
|
|
@ -139,11 +143,11 @@ static unsigned char smbus_read_byte(unsigned char devAdr,
|
|||
{
|
||||
unsigned short i;
|
||||
unsigned char bData;
|
||||
unsigned char sts;
|
||||
unsigned char sts = 0;
|
||||
|
||||
/* clear host status */
|
||||
outb(0xff, SMBUS_IO_BASE);
|
||||
|
||||
|
||||
/* check SMBUS ready */
|
||||
for ( i = 0; i < 0xFFFF; i++ )
|
||||
if ( (inb(SMBUS_IO_BASE) & 0x01) == 0 )
|
||||
|
|
|
|||
Loading…
Reference in New Issue