diff --git a/src/mainboard/system76/lemp9/romstage.c b/src/mainboard/system76/lemp9/romstage.c
index 1af8ce6633..3b9c896f1b 100644
--- a/src/mainboard/system76/lemp9/romstage.c
+++ b/src/mainboard/system76/lemp9/romstage.c
@@ -16,36 +16,6 @@ static const struct cnl_mb_cfg memcfg = {
 	},
 	.spd[3] = {.read_type = NOT_EXISTING},
 
-	/*
-	 * For each channel, there are 3 sets of DQ byte mappings,
-	 * where each set has a package 0 and a package 1 value (package 0
-	 * represents the first 64-bit lpddr4 chip combination, and package 1
-	 * represents the second 64-bit lpddr4 chip combination).
-	 * The first three sets are for CLK, CMD, and CTL.
-	 * The fsp package actually expects 6 sets, but the last 3 sets are
-	 * not used in CNL, so we only define the three sets that are used
-	 * and let the meminit_lpddr4() routine take care of clearing the
-	 * unused fields for the caller.
-	 */
-	.dq_map[DDR_CH0] = {
-		{0x0F, 0xF0}, {0x00, 0xF0}, {0x0F, 0xF0},
-		//{0x0F, 0x00}, {0xFF, 0x00}, {0xFF, 0x00}
-	},
-	.dq_map[DDR_CH1] = {
-		{0x33, 0xCC}, {0x00, 0xCC}, {0x33, 0xCC},
-		//{0x33, 0x00}, {0xFF, 0x00}, {0xFF, 0x00}
-	},
-
-	/*
-	 * DQS CPU<>DRAM map Ch0 and Ch1.  Each array entry represents a
-	 * mapping of a dq bit on the CPU to the bit it's connected to on
-	 * the memory part.  The array index represents the dqs bit number
-	 * on the memory part, and the values in the array represent which
-	 * pin on the CPU that DRAM pin connects to.
-	 */
-	.dqs_map[DDR_CH0] = {0, 1, 2, 3, 4, 5, 6, 7},
-	.dqs_map[DDR_CH1] = {1, 0, 2, 3, 4, 5, 6, 7},
-
 	/*
 	 * Rcomp resistor values.  These values represent the resistance in
 	 * ohms of the three rcomp resistors attached to the DDR_COMP_0,
@@ -53,10 +23,7 @@ static const struct cnl_mb_cfg memcfg = {
 	 */
 	.rcomp_resistor = { 121, 81, 100 },
 
-	/*
-	 * Rcomp target values.  These will typically be the following
-	 * values for Cannon Lake : { 80, 40, 40, 40, 30 }
-	 */
+	/* Rcomp target values */
 	.rcomp_targets = { 100, 40, 20, 20, 26 },
 
 	/*