1) Initialize BSP fixed MTRRs to match AP fixed MTRR initialization.
2) Remove coreboot variable MTRR initialization because AMD reference code handles it. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6570 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -62,6 +62,7 @@ static void model_14_init(device_t dev)
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u8 i;
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u8 i;
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msr_t msr;
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msr_t msr;
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int msrno;
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struct node_core_id id;
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struct node_core_id id;
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#if CONFIG_LOGICAL_CPUS == 1
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#if CONFIG_LOGICAL_CPUS == 1
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u32 siblings;
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u32 siblings;
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@ -70,12 +71,24 @@ static void model_14_init(device_t dev)
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// id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */
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// id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */
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// printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
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// printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
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/* Turn on caching if we haven't already */
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disable_cache ();
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x86_enable_cache();
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/* Enable access to AMD RdDram and WrDram extension bits */
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amd_setup_mtrrs();
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msr = rdmsr(SYSCFG_MSR);
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x86_mtrr_check();
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msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
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wrmsr(SYSCFG_MSR, msr);
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disable_cache();
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// BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs
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msr.lo = msr.hi = 0;
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wrmsr (0x259, msr);
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msr.lo = msr.hi = 0x1e1e1e1e;
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for (msrno = 0x268; msrno <= 0x26f; msrno++)
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wrmsr (msrno, msr);
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/* disable access to AMD RdDram and WrDram extension bits */
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msr = rdmsr(SYSCFG_MSR);
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msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
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wrmsr(SYSCFG_MSR, msr);
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enable_cache ();
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/* zero the machine check error status registers */
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/* zero the machine check error status registers */
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msr.lo = 0;
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msr.lo = 0;
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@ -84,8 +97,6 @@ static void model_14_init(device_t dev)
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wrmsr(MCI_STATUS + (i * 4), msr);
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wrmsr(MCI_STATUS + (i * 4), msr);
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}
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}
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enable_cache();
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/* Enable the local cpu apics */
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/* Enable the local cpu apics */
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setup_lapic();
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setup_lapic();
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