From a7305c19e649e07053ce321fd0e8a12a0a277332 Mon Sep 17 00:00:00 2001 From: Gaggery Tsai Date: Mon, 14 Feb 2022 23:27:52 -0800 Subject: [PATCH] mb/google/brya/var/vell: Correct the DQ mapping This patch corrects the DQ mapping and enable ECT. In Vell design, the DQS is swapped in Mc0.ch1, Mc0.ch3, Mc1.ch0, Mc1.ch1 and Mc1.ch2 but the DQ mappings are not swapped and that causes ECT training failure. BUT=b:208719081 TEST=emerge-brya coreboot chromeos-bootimage && ensure the system passes ECT training and all the way booting to the OS. Signed-off-by: Gaggery Tsai Change-Id: Idd2ad16151f0b2b93b00295b75a66ba65cba23cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/61981 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- .../google/brya/variants/vell/memory.c | 22 +++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/src/mainboard/google/brya/variants/vell/memory.c b/src/mainboard/google/brya/variants/vell/memory.c index 545013f2aa..fd36c5dda3 100644 --- a/src/mainboard/google/brya/variants/vell/memory.c +++ b/src/mainboard/google/brya/variants/vell/memory.c @@ -23,28 +23,28 @@ static const struct mb_cfg baseboard_memcfg = { .dq1 = { 9, 13, 12, 8, 15, 10, 14, 11, }, }, .ddr1 = { - .dq0 = { 0, 2, 1, 3, 7, 5, 6, 4, }, - .dq1 = { 10, 8, 11, 9, 13, 15, 14, 12, }, + .dq1 = { 0, 2, 1, 3, 7, 5, 6, 4, }, + .dq0 = { 10, 8, 11, 9, 13, 15, 14, 12, }, }, .ddr2 = { .dq0 = { 3, 7, 2, 6, 4, 1, 5, 0, }, .dq1 = { 12, 14, 15, 13, 11, 8, 10, 9, }, }, .ddr3 = { - .dq0 = { 7, 6, 4, 5, 0, 3, 1, 2, }, - .dq1 = { 9, 13, 8, 12, 15, 10, 14, 11, }, + .dq1 = { 7, 6, 4, 5, 0, 3, 1, 2, }, + .dq0 = { 9, 13, 8, 12, 15, 10, 14, 11, }, }, .ddr4 = { - .dq0 = { 7, 5, 4, 6, 2, 0, 1, 3, }, - .dq1 = { 15, 14, 12, 13, 10, 9, 8, 11, }, + .dq1 = { 7, 5, 4, 6, 2, 0, 1, 3, }, + .dq0 = { 15, 14, 12, 13, 10, 9, 8, 11, }, }, .ddr5 = { - .dq0 = { 3, 7, 2, 6, 0, 4, 5, 1, }, - .dq1 = { 9, 10, 11, 8, 12, 15, 13, 14, }, + .dq1 = { 3, 7, 2, 6, 0, 4, 5, 1, }, + .dq0 = { 9, 10, 11, 8, 12, 15, 13, 14, }, }, .ddr6 = { - .dq0 = { 1, 0, 3, 2, 7, 5, 4, 6, }, - .dq1 = { 11, 8, 10, 9, 12, 14, 13, 15, }, + .dq1 = { 1, 0, 3, 2, 7, 5, 4, 6, }, + .dq0 = { 11, 8, 10, 9, 12, 14, 13, 15, }, }, .ddr7 = { .dq0 = { 3, 2, 1, 0, 7, 5, 6, 4, }, @@ -64,7 +64,7 @@ static const struct mb_cfg baseboard_memcfg = { .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, }, - .ect = false, /* Early Command Training */ + .ect = true, /* Early Command Training */ .UserBd = BOARD_TYPE_ULT_ULX_T4, .lp5x_config = {