mainboard/supermicro/h8qme_fam10: Fix indentations and spelling
Change-Id: I49c5d39a674351f7375fb762fc9ef4a3700d7c87 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9177 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Timothy Pearson
Aaron Durbin
parent
9eebbd4151
commit
a73dcbe736
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@ -50,10 +50,11 @@
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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#define DUMMY_DEV PNP_DEV(0x2e, 0)
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static inline void activate_spd_rom(const struct mem_controller *ctrl)
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{
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#define SMBUS_SWITCH1 0x70
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#define SMBUS_SWITCH2 0x72
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static inline void activate_spd_rom(const struct mem_controller *ctrl)
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{
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smbus_send_byte(SMBUS_SWITCH1, 5 & 0x0f);
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smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f);
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}
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@ -77,36 +78,36 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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static void sio_setup(void)
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{
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uint32_t dword;
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uint8_t byte;
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enable_smbus();
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uint32_t dword;
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uint8_t byte;
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enable_smbus();
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// smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
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smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
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byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
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byte |= 0x20;
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pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
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byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
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byte |= 0x20;
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pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
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dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
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dword |= (1<<0);
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pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
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dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
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dword |= (1<<0);
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pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
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dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
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dword |= (1<<16);
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pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
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dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
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dword |= (1<<16);
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pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
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}
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static const u8 spd_addr[] = {
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//first node
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/* first node */
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RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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#if CONFIG_MAX_PHYSICAL_CPUS > 1
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//second node
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/* second node */
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RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
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#endif
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#if CONFIG_MAX_PHYSICAL_CPUS > 2
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//third node
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/* third node */
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RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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//forth node
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/* fourth node */
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RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0,
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#endif
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};
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@ -183,12 +184,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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sio_setup();
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}
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post_code(0x30);
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post_code(0x30);
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if (bist == 0)
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bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
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post_code(0x32);
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post_code(0x32);
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w83627hf_set_clksel_48(DUMMY_DEV);
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winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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@ -200,113 +201,113 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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/* Halt if there was a built in self test failure */
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report_bist_failure(bist);
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val = cpuid_eax(1);
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printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
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printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
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printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
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printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
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val = cpuid_eax(1);
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printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
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printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
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printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
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printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
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/* Setup sysinfo defaults */
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set_sysinfo_in_ram(0);
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/* Setup sysinfo defaults */
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set_sysinfo_in_ram(0);
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update_microcode(val);
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update_microcode(val);
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post_code(0x33);
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post_code(0x33);
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cpuSetAMDMSR();
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post_code(0x34);
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cpuSetAMDMSR();
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post_code(0x34);
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amd_ht_init(sysinfo);
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post_code(0x35);
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amd_ht_init(sysinfo);
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post_code(0x35);
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/* Setup nodes PCI space and start core 0 AP init. */
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finalize_node_setup(sysinfo);
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/* Setup nodes PCI space and start core 0 AP init. */
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finalize_node_setup(sysinfo);
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/* Setup any mainboard PCI settings etc. */
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setup_mb_resource_map();
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post_code(0x36);
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/* Setup any mainboard PCI settings etc. */
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setup_mb_resource_map();
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post_code(0x36);
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/* wait for all the APs core0 started by finalize_node_setup. */
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/* FIXME: A bunch of cores are going to start output to serial at once.
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* It would be nice to fixup prink spinlocks for ROM XIP mode.
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* I think it could be done by putting the spinlock flag in the cache
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* of the BSP located right after sysinfo.
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*/
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/* wait for all the APs core0 started by finalize_node_setup. */
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/* FIXME: A bunch of cores are going to start output to serial at once.
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* It would be nice to fixup prink spinlocks for ROM XIP mode.
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* I think it could be done by putting the spinlock flag in the cache
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* of the BSP located right after sysinfo.
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*/
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wait_all_core0_started();
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wait_all_core0_started();
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#if CONFIG_LOGICAL_CPUS
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/* Core0 on each node is configured. Now setup any additional cores. */
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printk(BIOS_DEBUG, "start_other_cores()\n");
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start_other_cores();
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post_code(0x37);
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wait_all_other_cores_started(bsp_apicid);
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/* Core0 on each node is configured. Now setup any additional cores. */
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printk(BIOS_DEBUG, "start_other_cores()\n");
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start_other_cores();
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post_code(0x37);
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wait_all_other_cores_started(bsp_apicid);
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#endif
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post_code(0x38);
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post_code(0x38);
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#if CONFIG_SET_FIDVID
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msr = rdmsr(0xc0010071);
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printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
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msr = rdmsr(0xc0010071);
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printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
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/* FIXME: The sb fid change may survive the warm reset and only
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* need to be done once.*/
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/* FIXME: The sb fid change may survive the warm reset and only
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* need to be done once.*/
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enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
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post_code(0x39);
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enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
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post_code(0x39);
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if (!warm_reset_detect(0)) { // BSP is node 0
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init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
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} else {
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init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
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}
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if (!warm_reset_detect(0)) { // BSP is node 0
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init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
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} else {
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init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
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}
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post_code(0x3A);
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post_code(0x3A);
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/* show final fid and vid */
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msr=rdmsr(0xc0010071);
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printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
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/* show final fid and vid */
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msr=rdmsr(0xc0010071);
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printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
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#endif
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init_timer(); // Need to use TMICT to synchronize FID/VID
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wants_reset = mcp55_early_setup_x();
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wants_reset = mcp55_early_setup_x();
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/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
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if (!warm_reset_detect(0)) {
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printk(BIOS_INFO, "...WARM RESET...\n\n\n");
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soft_reset();
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die("After soft_reset_x - shouldn't see this message!!!\n");
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}
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/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
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if (!warm_reset_detect(0)) {
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printk(BIOS_INFO, "...WARM RESET...\n\n\n");
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soft_reset();
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die("After soft_reset_x - shouldn't see this message!!!\n");
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}
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if (wants_reset)
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printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
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if (wants_reset)
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printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
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post_code(0x3B);
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post_code(0x3B);
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/* It's the time to set ctrl in sysinfo now; */
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printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
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fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
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/* It's the time to set ctrl in sysinfo now; */
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printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
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fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
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post_code(0x3D);
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post_code(0x3D);
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//printk(BIOS_DEBUG, "enable_smbus()\n");
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// enable_smbus(); /* enable in sio_setup */
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// printk(BIOS_DEBUG, "enable_smbus()\n");
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// enable_smbus(); /* enable in sio_setup */
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post_code(0x40);
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post_code(0x40);
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timestamp_add_now(TS_BEFORE_INITRAM);
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printk(BIOS_DEBUG, "raminit_amdmct()\n");
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raminit_amdmct(sysinfo);
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printk(BIOS_DEBUG, "raminit_amdmct()\n");
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raminit_amdmct(sysinfo);
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timestamp_add_now(TS_AFTER_INITRAM);
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cbmem_initialize_empty();
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post_code(0x41);
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cbmem_initialize_empty();
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post_code(0x41);
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amdmct_cbmem_store_info(sysinfo);
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amdmct_cbmem_store_info(sysinfo);
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timestamp_add_now(TS_END_ROMSTAGE);
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post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
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post_code(0x42); // Should never see this post code.
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post_cache_as_ram(); /* BSP switch stack to ram, copy then execute CB. */
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post_code(0x42); /* Should never see this post code. */
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}
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/**
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