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mainboard/supermicro/h8qme_fam10: Fix indentations and spelling 

Change-Id: I49c5d39a674351f7375fb762fc9ef4a3700d7c87
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9177
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Timothy Pearson 2015-03-31 11:54:03 -05:00 committed by Aaron Durbin
parent 9eebbd4151
commit a73dcbe736
1 changed files with 91 additions and 90 deletions
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17
src/mainboard/supermicro/h8qme_fam10/romstage.c
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@ -50,10 +50,11 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#define DUMMY_DEV PNP_DEV(0x2e, 0) #define DUMMY_DEV PNP_DEV(0x2e, 0)
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_SWITCH1 0x70 #define SMBUS_SWITCH1 0x70
#define SMBUS_SWITCH2 0x72 #define SMBUS_SWITCH2 0x72
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
smbus_send_byte(SMBUS_SWITCH1, 5 & 0x0f); smbus_send_byte(SMBUS_SWITCH1, 5 & 0x0f);
smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f); smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f);
} }
@ -97,16 +98,16 @@ static void sio_setup(void)
} }
static const u8 spd_addr[] = { static const u8 spd_addr[] = {
//first node /* first node */
RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1 #if CONFIG_MAX_PHYSICAL_CPUS > 1
//second node /* second node */
RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
#endif #endif
#if CONFIG_MAX_PHYSICAL_CPUS > 2 #if CONFIG_MAX_PHYSICAL_CPUS > 2
//third node /* third node */
RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
//forth node /* fourth node */
RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0, RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0,
#endif #endif
}; };
@ -305,8 +306,8 @@ post_code(0x40);
timestamp_add_now(TS_END_ROMSTAGE); timestamp_add_now(TS_END_ROMSTAGE);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_cache_as_ram(); /* BSP switch stack to ram, copy then execute CB. */
post_code(0x42); // Should never see this post code. post_code(0x42); /* Should never see this post code. */
} }
/** /**