mainboard/supermicro/h8qme_fam10: Fix indentations and spelling
Change-Id: I49c5d39a674351f7375fb762fc9ef4a3700d7c87 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9177 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
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@ -50,10 +50,11 @@
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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#define DUMMY_DEV PNP_DEV(0x2e, 0)
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static inline void activate_spd_rom(const struct mem_controller *ctrl)
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{
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#define SMBUS_SWITCH1 0x70
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#define SMBUS_SWITCH2 0x72
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static inline void activate_spd_rom(const struct mem_controller *ctrl)
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{
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smbus_send_byte(SMBUS_SWITCH1, 5 & 0x0f);
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smbus_send_byte(SMBUS_SWITCH2, (5 >> 4) & 0x0f);
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}
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@ -97,16 +98,16 @@ static void sio_setup(void)
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}
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static const u8 spd_addr[] = {
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//first node
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/* first node */
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RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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#if CONFIG_MAX_PHYSICAL_CPUS > 1
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//second node
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/* second node */
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RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
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#endif
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#if CONFIG_MAX_PHYSICAL_CPUS > 2
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//third node
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/* third node */
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RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
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//forth node
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/* fourth node */
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RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0,
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#endif
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};
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@ -305,8 +306,8 @@ post_code(0x40);
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timestamp_add_now(TS_END_ROMSTAGE);
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post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
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post_code(0x42); // Should never see this post code.
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post_cache_as_ram(); /* BSP switch stack to ram, copy then execute CB. */
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post_code(0x42); /* Should never see this post code. */
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}
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/**
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