failoverR.diff: Revert my failover change since Kconfig only supports fallback.
kconfig_s2892.dif: Add support for Tyan s2891, s2892, and s2895 to Kconfig. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4656 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson
parent
45bb25f36f
commit
a74ae635ca
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@ -23,6 +23,9 @@ choice
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depends on VENDOR_TYAN
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source "src/mainboard/tyan/s1846/Kconfig"
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source "src/mainboard/tyan/s2891/Kconfig"
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source "src/mainboard/tyan/s2892/Kconfig"
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source "src/mainboard/tyan/s2895/Kconfig"
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endchoice
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@ -0,0 +1,73 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2008 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or
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## modify it under the terms of the GNU General Public License as
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## published by the Free Software Foundation; version 2 of
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## the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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## MA 02110-1301 USA
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##
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##
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## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
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##
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driver-y += mainboard.o
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#needed by irq_tables and mptable and acpi_tables
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obj-y += get_bus_conf.o
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obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
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obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
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obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o
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obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o
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#driver-y += ../../../drivers/i2c/i2cmux/i2cmux.o
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# This is part of the conversion to init-obj and away from included code.
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initobj-y += crt0.o
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# FIXME in $(top)/Makefile
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crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
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crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
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crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
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crt0-y += ../../../../src/southbridge/nvidia/ck804/id.inc
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crt0-y += ../../../../src/southbridge/nvidia/ck804/romstrap.inc
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crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
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crt0-y += auto.inc
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ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
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ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
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ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
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ldscript-y += ../../../../src/southbridge/nvidia/ck804/id.lds
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ldscript-y += ../../../../src/southbridge/nvidia/ck804/romstrap.lds
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ldscript-y += ../../../../src/arch/i386/lib/failover.lds
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ifdef POST_EVALUATION
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MAINBOARD_OPTIONS= -DCONFIG_AP_IN_SIPI_WAIT=0
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$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.dsl
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iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.dsl
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mv dsdt.hex $@
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$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
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$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
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$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h
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$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@
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perl -e 's/\.rodata/.rom.data/g' -pi $@
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perl -e 's/\.text/.section .rom.text/g' -pi $@
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endif
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@ -0,0 +1,142 @@
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config BOARD_TYAN_S2891
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bool "Tyan Thunder K8SRE S2891"
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select ARCH_X86
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select CPU_AMD_K8
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select CPU_AMD_SOCKET_940
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select NORTHBRIDGE_AMD_AMDK8
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select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
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select SOUTHBRIDGE_NVIDIA_CK804
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select SOUTHBRIDGE_AMD_AMD8131
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select SUPERIO_WINBOND_W83627HF
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select PIRQ_TABLE
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config MAINBOARD_DIR
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string
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default tyan/s2891
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depends on BOARD_TYAN_S2891
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config APIC_ID_OFFSET
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hex
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default 8
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depends on BOARD_TYAN_S2891
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config SB_HT_CHAIN_ON_BUS0
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int
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default 2
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depends on BOARD_TYAN_S2891
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config LB_CKS_RANGE_END
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int
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default 122
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depends on BOARD_TYAN_S2891
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config LB_CKS_LOC
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int
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default 123
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depends on BOARD_TYAN_S2891
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config MAINBOARD_PART_NUMBER
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string
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default "s2891"
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depends on BOARD_TYAN_S2891
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config CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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hex
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default 0x2891
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depends on BOARD_TYAN_S2891
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config USE_FAILOVER_IMAGE
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bool
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default n
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depends on BOARD_TYAN_S2891
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config HW_MEM_HOLE_SIZEK
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hex
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default 0x100000
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depends on BOARD_TYAN_S2891
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config MEM_TRAIN_SEQ
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bool
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default n
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depends on BOARD_TYAN_S2891
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config HAVE_FAILOVER_BOOT
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bool
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default n
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depends on BOARD_TYAN_S2891
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config USE_FAILOVER_IMAGE
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bool
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default n
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depends on BOARD_TYAN_S2891
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config MAX_CPUS
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int
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default 4
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depends on BOARD_TYAN_S2891
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config MAX_PHYSICAL_CPUS
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int
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default 2
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depends on BOARD_TYAN_S2891
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config MEM_TRAIN_SEQ
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bool
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default n
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depends on BOARD_TYAN_S2891
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config AP_CODE_IN_CAR
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bool
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default n
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depends on BOARD_TYAN_S2891
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config HW_MEM_HOLE_SIZE_AUTO_INC
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bool
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default n
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depends on BOARD_TYAN_S2891
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config HT_CHAIN_UNITID_BASE
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hex
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default 0
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depends on BOARD_TYAN_S2891
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x20
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depends on BOARD_TYAN_S2891
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config USE_INIT
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bool
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default n
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depends on BOARD_TYAN_S2891
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config SERIAL_CPU_INIT
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bool
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default y
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depends on BOARD_TYAN_S2891
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config AP_CODE_IN_CAR
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bool
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default y
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depends on BOARD_TYAN_S2891
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config WAIT_BEFORE_CPUS_INIT
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bool
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default n
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depends on BOARD_TYAN_S2891
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config SB_HT_CHAIN_ON_BUS0
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int
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default 2
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depends on BOARD_TYAN_S2891
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config SB_HT_CHAIN_UNITID_OFFSET_ONLY
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bool
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default n
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depends on BOARD_TYAN_S2891
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config HAVE_ACPI_TABLES
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bool "Generate ACPI tables"
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default y
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depends on BOARD_TYAN_S2891
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@ -0,0 +1 @@
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include $(src)/mainboard/tyan/Makefile.s289x.inc
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@ -0,0 +1,142 @@
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config BOARD_TYAN_S2892
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bool "Tyan Thunder K8SE S2892"
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select ARCH_X86
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select CPU_AMD_K8
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select CPU_AMD_SOCKET_940
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select NORTHBRIDGE_AMD_AMDK8
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select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
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select SOUTHBRIDGE_NVIDIA_CK804
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select SOUTHBRIDGE_AMD_AMD8131
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select SUPERIO_WINBOND_W83627HF
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select PIRQ_TABLE
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config MAINBOARD_DIR
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string
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default tyan/s2892
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depends on BOARD_TYAN_S2892
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config APIC_ID_OFFSET
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hex
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default 8
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depends on BOARD_TYAN_S2892
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config SB_HT_CHAIN_ON_BUS0
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int
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default 2
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depends on BOARD_TYAN_S2892
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config LB_CKS_RANGE_END
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int
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default 122
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depends on BOARD_TYAN_S2892
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config LB_CKS_LOC
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int
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default 123
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depends on BOARD_TYAN_S2892
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config MAINBOARD_PART_NUMBER
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string
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default "s2892"
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depends on BOARD_TYAN_S2892
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config CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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hex
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default 0x2892
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depends on BOARD_TYAN_S2892
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config USE_FAILOVER_IMAGE
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bool
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default n
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depends on BOARD_TYAN_S2892
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config HW_MEM_HOLE_SIZEK
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hex
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default 0x100000
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depends on BOARD_TYAN_S2892
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config MEM_TRAIN_SEQ
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bool
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default n
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depends on BOARD_TYAN_S2892
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config HAVE_FAILOVER_BOOT
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bool
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default n
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depends on BOARD_TYAN_S2892
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config USE_FAILOVER_IMAGE
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bool
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default n
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depends on BOARD_TYAN_S2892
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config MAX_CPUS
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int
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default 4
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depends on BOARD_TYAN_S2892
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config MAX_PHYSICAL_CPUS
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int
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default 2
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depends on BOARD_TYAN_S2892
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config MEM_TRAIN_SEQ
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bool
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default n
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depends on BOARD_TYAN_S2892
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config AP_CODE_IN_CAR
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bool
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default n
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depends on BOARD_TYAN_S2892
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config HW_MEM_HOLE_SIZE_AUTO_INC
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bool
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default n
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depends on BOARD_TYAN_S2892
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config HT_CHAIN_UNITID_BASE
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hex
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default 0
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depends on BOARD_TYAN_S2892
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x20
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depends on BOARD_TYAN_S2892
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config USE_INIT
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bool
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default n
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depends on BOARD_TYAN_S2892
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config SERIAL_CPU_INIT
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bool
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default y
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depends on BOARD_TYAN_S2892
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config AP_CODE_IN_CAR
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bool
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default y
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depends on BOARD_TYAN_S2892
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config WAIT_BEFORE_CPUS_INIT
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bool
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default n
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depends on BOARD_TYAN_S2892
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config SB_HT_CHAIN_ON_BUS0
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int
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default 2
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depends on BOARD_TYAN_S2892
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config SB_HT_CHAIN_UNITID_OFFSET_ONLY
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bool
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default n
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depends on BOARD_TYAN_S2892
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config HAVE_ACPI_TABLES
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bool "Generate ACPI tables"
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default y
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depends on BOARD_TYAN_S2892
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@ -0,0 +1,3 @@
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include $(src)/mainboard/tyan/Makefile.s289x.inc
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driver-y += ../../../drivers/i2c/adm1027/adm1027.o
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@ -29,25 +29,10 @@ if CONFIG_HAVE_ACPI_TABLES
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end
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if CONFIG_USE_INIT
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if CONFIG_USE_FAILOVER_IMAGE
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makerule ./auto.o
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depends "$(CONFIG_MAINBOARD)/failover.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/failover.c -o $@"
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end
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else
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makerule ./auto.o
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depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
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end
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end
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else #CONFIG_USE_INIT
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if CONFIG_USE_FAILOVER_IMAGE
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makerule ./auto.inc
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depends "$(CONFIG_MAINBOARD)/failover.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/failover.c -o $@"
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action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
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action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
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end
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else
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makerule ./auto.inc
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depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
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@ -56,32 +41,51 @@ else
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action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
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end
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end
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end #CONFIG_USE_INIT
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##
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## Build our 16 bit and 32 bit coreboot entry code
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##
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if CONFIG_USE_FAILOVER_IMAGE
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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if CONFIG_HAVE_FAILOVER_BOOT
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if CONFIG_USE_FAILOVER_IMAGE
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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end
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else
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if CONFIG_USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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end
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end
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mainboardinit cpu/x86/32bit/entry32.inc
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if CONFIG_USE_INIT
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ldscript /cpu/x86/32bit/entry32.lds
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end
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if CONFIG_USE_INIT
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ldscript /cpu/amd/car/cache_as_ram.lds
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end
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##
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## Build our reset vector (This is where coreboot is entered)
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##
|
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if CONFIG_USE_FAILOVER_IMAGE
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if CONFIG_HAVE_FAILOVER_BOOT
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if CONFIG_USE_FAILOVER_IMAGE
|
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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else
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if CONFIG_USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
|
||||
end
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||||
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##
|
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@ -93,9 +97,16 @@ ldscript /southbridge/nvidia/ck804/id.lds
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##
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## ROMSTRAP table for CK804
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##
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if CONFIG_USE_FAILOVER_IMAGE
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mainboardinit southbridge/nvidia/ck804/romstrap.inc
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ldscript /southbridge/nvidia/ck804/romstrap.lds
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if CONFIG_HAVE_FAILOVER_BOOT
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if CONFIG_USE_FAILOVER_IMAGE
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mainboardinit southbridge/nvidia/ck804/romstrap.inc
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ldscript /southbridge/nvidia/ck804/romstrap.lds
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end
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else
|
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if CONFIG_USE_FALLBACK_IMAGE
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mainboardinit southbridge/nvidia/ck804/romstrap.inc
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ldscript /southbridge/nvidia/ck804/romstrap.lds
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||||
end
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||||
end
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||||
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##
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@ -108,8 +119,14 @@ end
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### Things are delicate and we test to see if we should
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### failover to another image.
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||||
###
|
||||
if CONFIG_USE_FAILOVER_IMAGE
|
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ldscript /arch/i386/lib/failover_failover.lds
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if CONFIG_HAVE_FAILOVER_BOOT
|
||||
if CONFIG_USE_FAILOVER_IMAGE
|
||||
ldscript /arch/i386/lib/failover_failover.lds
|
||||
end
|
||||
else
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
end
|
||||
end
|
||||
|
||||
##
|
||||
|
|
|
|||
|
|
@ -0,0 +1,142 @@
|
|||
config BOARD_TYAN_S2895
|
||||
bool "Tyan Thunder K8WE S2895"
|
||||
select ARCH_X86
|
||||
select CPU_AMD_K8
|
||||
select CPU_AMD_SOCKET_940
|
||||
select NORTHBRIDGE_AMD_AMDK8
|
||||
select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
|
||||
select SOUTHBRIDGE_NVIDIA_CK804
|
||||
select SOUTHBRIDGE_AMD_AMD8131
|
||||
select SUPERIO_SMSC_LPC47B397
|
||||
select PIRQ_TABLE
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default tyan/s2895
|
||||
depends on BOARD_TYAN_S2895
|
||||
|
||||
config APIC_ID_OFFSET
|
||||
hex
|
||||
default 8
|
||||
depends on BOARD_TYAN_S2895
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 2
|
||||
depends on BOARD_TYAN_S2895
|
||||
|
||||
config LB_CKS_RANGE_END
|
||||
int
|
||||
default 122
|
||||
depends on BOARD_TYAN_S2895
|
||||
|
||||
config LB_CKS_LOC
|
||||
int
|
||||
default 123
|
||||
depends on BOARD_TYAN_S2895
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "s2895"
|
||||
depends on BOARD_TYAN_S2895
|
||||
|
||||
config CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
||||
hex
|
||||
default 0x2895
|
||||
depends on BOARD_TYAN_S2895
|
||||
|
||||
config USE_FAILOVER_IMAGE
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_TYAN_S2895
|
||||
|
||||
config HW_MEM_HOLE_SIZEK
|
||||
hex
|
||||
default 0x100000
|
||||
depends on BOARD_TYAN_S2895
|
||||
|
||||
config MEM_TRAIN_SEQ
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_TYAN_S2895
|
||||
|
||||
config HAVE_FAILOVER_BOOT
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_TYAN_S2895
|
||||
|
||||
config USE_FAILOVER_IMAGE
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_TYAN_S2895
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 4
|
||||
depends on BOARD_TYAN_S2895
|
||||
|
||||
config MAX_PHYSICAL_CPUS
|
||||
int
|
||||
default 2
|
||||
depends on BOARD_TYAN_S2895
|
||||
|
||||
config MEM_TRAIN_SEQ
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_TYAN_S2895
|
||||
|
||||
config AP_CODE_IN_CAR
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_TYAN_S2895
|
||||
|
||||
config HW_MEM_HOLE_SIZE_AUTO_INC
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_TYAN_S2895
|
||||
|
||||
config HT_CHAIN_UNITID_BASE
|
||||
hex
|
||||
default 0
|
||||
depends on BOARD_TYAN_S2895
|
||||
|
||||
config HT_CHAIN_END_UNITID_BASE
|
||||
hex
|
||||
default 0x20
|
||||
depends on BOARD_TYAN_S2895
|
||||
|
||||
config USE_INIT
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_TYAN_S2895
|
||||
|
||||
config SERIAL_CPU_INIT
|
||||
bool
|
||||
default y
|
||||
depends on BOARD_TYAN_S2895
|
||||
|
||||
config AP_CODE_IN_CAR
|
||||
bool
|
||||
default y
|
||||
depends on BOARD_TYAN_S2895
|
||||
|
||||
config WAIT_BEFORE_CPUS_INIT
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_TYAN_S2895
|
||||
|
||||
config SB_HT_CHAIN_ON_BUS0
|
||||
int
|
||||
default 2
|
||||
depends on BOARD_TYAN_S2895
|
||||
|
||||
config SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
bool
|
||||
default n
|
||||
depends on BOARD_TYAN_S2895
|
||||
|
||||
config HAVE_ACPI_TABLES
|
||||
bool "Generate ACPI tables"
|
||||
default y
|
||||
depends on BOARD_TYAN_S2895
|
||||
|
||||
|
|
@ -0,0 +1 @@
|
|||
include $(src)/mainboard/tyan/Makefile.s289x.inc
|
||||
|
|
@ -1,3 +1,4 @@
|
|||
#define ASSEMBLY 1
|
||||
#define __ROMCC__
|
||||
|
||||
#define K8_ALLOCATE_IO_RANGE 1
|
||||
|
|
@ -20,12 +21,11 @@
|
|||
#include "option_table.h"
|
||||
#include "pc80/mc146818rtc_early.c"
|
||||
|
||||
#define post_code(x) outb(x, 0x80)
|
||||
#if CONFIG_USE_FAILOVER_IMAGE==0
|
||||
#include "pc80/serial.c"
|
||||
#include "arch/i386/lib/console.c"
|
||||
#include "ram/ramtest.c"
|
||||
|
||||
|
||||
#include <cpu/amd/model_fxx_rev.h>
|
||||
|
||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||
|
|
@ -34,6 +34,8 @@
|
|||
#include "cpu/amd/model_fxx/apic_timer.c"
|
||||
#include "lib/delay.c"
|
||||
|
||||
#endif
|
||||
|
||||
#include "cpu/x86/lapic/boot_cpu.c"
|
||||
#include "northbridge/amd/amdk8/reset_test.c"
|
||||
#include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
|
||||
|
|
@ -42,6 +44,8 @@
|
|||
|
||||
#define SUPERIO_GPIO_IO_BASE 0x400
|
||||
|
||||
#if CONFIG_USE_FAILOVER_IMAGE==0
|
||||
|
||||
#include "cpu/x86/bist.h"
|
||||
|
||||
#include "northbridge/amd/amdk8/debug.c"
|
||||
|
|
@ -114,7 +118,116 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
|
||||
#include "cpu/amd/model_fxx/init_cpus.c"
|
||||
|
||||
#endif
|
||||
|
||||
#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
|
||||
|
||||
#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
|
||||
#include "northbridge/amd/amdk8/early_ht.c"
|
||||
|
||||
static void sio_setup(void)
|
||||
{
|
||||
|
||||
unsigned value;
|
||||
uint32_t dword;
|
||||
uint8_t byte;
|
||||
|
||||
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
|
||||
|
||||
byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
|
||||
byte |= 0x20;
|
||||
pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
|
||||
|
||||
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
|
||||
dword |= (1<<29)|(1<<0);
|
||||
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
|
||||
|
||||
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4);
|
||||
dword |= (1<<16);
|
||||
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
|
||||
|
||||
lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
|
||||
value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
|
||||
value &= 0xbf;
|
||||
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
|
||||
|
||||
}
|
||||
|
||||
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
unsigned last_boot_normal_x = last_boot_normal();
|
||||
|
||||
/* Is this a cpu only reset? or Is this a secondary cpu? */
|
||||
if ((cpu_init_detectedx) || (!boot_cpu())) {
|
||||
if (last_boot_normal_x) {
|
||||
goto normal_image;
|
||||
} else {
|
||||
goto fallback_image;
|
||||
}
|
||||
}
|
||||
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
|
||||
enumerate_ht_chain();
|
||||
|
||||
sio_setup();
|
||||
|
||||
/* Setup the ck804 */
|
||||
ck804_enable_rom();
|
||||
|
||||
/* Is this a deliberate reset by the bios */
|
||||
// post_code(0x22);
|
||||
if (bios_reset_detected() && last_boot_normal_x) {
|
||||
goto normal_image;
|
||||
}
|
||||
/* This is the primary cpu how should I boot? */
|
||||
else if (do_normal_boot()) {
|
||||
goto normal_image;
|
||||
}
|
||||
else {
|
||||
goto fallback_image;
|
||||
}
|
||||
normal_image:
|
||||
// post_code(0x23);
|
||||
__asm__ volatile ("jmp __normal_image"
|
||||
: /* outputs */
|
||||
: "a" (bist), "b"(cpu_init_detectedx) /* inputs */
|
||||
);
|
||||
|
||||
fallback_image:
|
||||
// post_code(0x25);
|
||||
#if CONFIG_HAVE_FAILOVER_BOOT==1
|
||||
__asm__ volatile ("jmp __fallback_image"
|
||||
: /* outputs */
|
||||
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
|
||||
)
|
||||
#endif
|
||||
;
|
||||
}
|
||||
#endif
|
||||
|
||||
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
#if CONFIG_HAVE_FAILOVER_BOOT==1
|
||||
#if CONFIG_USE_FAILOVER_IMAGE==1
|
||||
failover_process(bist, cpu_init_detectedx);
|
||||
#else
|
||||
real_main(bist, cpu_init_detectedx);
|
||||
#endif
|
||||
#else
|
||||
#if CONFIG_USE_FALLBACK_IMAGE == 1
|
||||
failover_process(bist, cpu_init_detectedx);
|
||||
#endif
|
||||
real_main(bist, cpu_init_detectedx);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if CONFIG_USE_FAILOVER_IMAGE==0
|
||||
|
||||
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
static const uint16_t spd_addr [] = {
|
||||
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
|
||||
|
|
@ -135,7 +248,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
bsp_apicid = init_cpus(cpu_init_detectedx);
|
||||
}
|
||||
|
||||
post_code(0x32);
|
||||
// post_code(0x32);
|
||||
|
||||
lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
uart_init();
|
||||
|
|
@ -197,3 +310,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
|
||||
post_cache_as_ram();
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,3 +1,14 @@
|
|||
config SOUTHBRIDGE_NVIDIA_CK804
|
||||
bool
|
||||
default n
|
||||
|
||||
config HAVE_HARD_RESET
|
||||
bool
|
||||
default y
|
||||
depends on SOUTHBRIDGE_NVIDIA_CK804
|
||||
|
||||
config IOAPIC
|
||||
bool
|
||||
default y
|
||||
depends on SOUTHBRIDGE_NVIDIA_CK804
|
||||
|
||||
|
|
|
|||
|
|
@ -24,11 +24,4 @@ romimage "fallback"
|
|||
payload __PAYLOAD__
|
||||
end
|
||||
|
||||
romimage "failover"
|
||||
option CONFIG_USE_FAILOVER_IMAGE=1
|
||||
option CONFIG_USE_FALLBACK_IMAGE=0
|
||||
option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
|
||||
option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
|
||||
end
|
||||
|
||||
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
|
||||
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
|
||||
|
|
|
|||
|
|
@ -7,80 +7,21 @@ mainboard tyan/s2895
|
|||
|
||||
# Tyan s2895
|
||||
romimage "normal"
|
||||
# 48K for SCSI FW
|
||||
# option CONFIG_ROM_SIZE = 475136
|
||||
# 48K for SCSI FW and 48K for ATI ROM
|
||||
# option CONFIG_ROM_SIZE = 425984
|
||||
# 64K for Etherboot
|
||||
# option CONFIG_ROM_SIZE = 458752
|
||||
# 64K for NIC option 48K for Raid option rom
|
||||
# option CONFIG_ROM_SIZE = 409600
|
||||
option CONFIG_USE_FAILOVER_IMAGE=0
|
||||
option CONFIG_USE_FALLBACK_IMAGE=0
|
||||
# option CONFIG_ROM_IMAGE_SIZE=0x11800
|
||||
# option CONFIG_ROM_IMAGE_SIZE=0x13800
|
||||
# option CONFIG_ROM_IMAGE_SIZE=0x15000
|
||||
option CONFIG_ROM_IMAGE_SIZE=0x20000
|
||||
# option CONFIG_ROM_IMAGE_SIZE=0x17800
|
||||
option CONFIG_XIP_ROM_SIZE=0x20000
|
||||
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
|
||||
# payload ../../../payloads/tg3--ide_disk.zelf
|
||||
# payload ../../../payloads/filo.elf
|
||||
# payload ../../../payloads/filo_mem.elf
|
||||
# payload ../../../payloads/filo.zelf
|
||||
# payload ../../../payloads/tg3.zelf
|
||||
# payload ../../../payloads/tg3--filo_hda2_vga.zelf
|
||||
# payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf
|
||||
# payload ../../../payloads/forcedeth_vga.zelf
|
||||
# payload ../../../payloads/forcedeth--filo_hda2_vga_5_4.zelf
|
||||
# payload ../../../../../../elf/ram0_2.5_2.6.11.tiny.elf
|
||||
# payload ../../../../../../elf/ram0_2.5_2.6.12.tiny.elf
|
||||
# payload ../../../payloads/tg3--filo_hda2_vga_5_4.zelf
|
||||
# payload ../../../payloads/tg3_vga.zelf
|
||||
# payload ../../../payloads/tg3--filo_hda2_vgax.zelf
|
||||
# payload ../../../payloads/tg3--filo_hda2_com2.zelf
|
||||
# payload ../../../payloads/e1000--filo.zelf
|
||||
# payload ../../../payloads/tg3--e1000--filo.zelf
|
||||
# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
|
||||
payload ../payload.elf
|
||||
end
|
||||
|
||||
romimage "fallback"
|
||||
option CONFIG_USE_FAILOVER_IMAGE=0
|
||||
option CONFIG_USE_FALLBACK_IMAGE=1
|
||||
# option CONFIG_ROM_IMAGE_SIZE=0x11800
|
||||
# option CONFIG_ROM_IMAGE_SIZE=0x13800
|
||||
# option CONFIG_ROM_IMAGE_SIZE=0x15000
|
||||
option CONFIG_ROM_IMAGE_SIZE=0x20000
|
||||
# option CONFIG_ROM_IMAGE_SIZE=0x17800
|
||||
option CONFIG_XIP_ROM_SIZE=0x20000
|
||||
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
|
||||
# payload ../../../payloads/tg3--ide_disk.zelf
|
||||
# payload ../../../payloads/filo.elf
|
||||
# payload ../../../payloads/filo_mem.elf
|
||||
# payload ../../../payloads/filo.zelf
|
||||
# payload ../../../payloads/tg3.zelf
|
||||
# payload ../../../payloads/tg3--filo_hda2_vga.zelf
|
||||
# payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf
|
||||
# payload ../../../payloads/forcedeth_vga.zelf
|
||||
# payload ../../../payloads/tg3--filo_hda2_vga_5_4.zelf
|
||||
# payload ../../../payloads/tg3_vga.zelf
|
||||
# payload ../../../payloads/tg3--filo_hda2_vgax.zelf
|
||||
# payload ../../../payloads/tg3--filo_hda2_com2.zelf
|
||||
# payload ../../../payloads/e1000--filo.zelf
|
||||
# payload ../../../payloads/tg3--e1000--filo.zelf
|
||||
# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
|
||||
payload ../payload.elf
|
||||
end
|
||||
|
||||
romimage "failover"
|
||||
option CONFIG_USE_FAILOVER_IMAGE=1
|
||||
option CONFIG_USE_FALLBACK_IMAGE=0
|
||||
option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
|
||||
option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
|
||||
option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
|
||||
end
|
||||
|
||||
|
||||
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
|
||||
#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
|
||||
buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
|
||||
|
|
|
|||
Loading…
Reference in New Issue