Overhaul speedstep code
This adds proper support for turbo and super-low-frequency modes. Calculation of the p-states has been rewritten and moved into an extra file speedstep.c so it can be used for non-acpi stuff like EMTTM table generation. It has been tested with a Core2Duo T9400 (Penryn) and a Core Duo T2300 (Yonah) processor. Change-Id: I5f7104fc921ba67d85794254f11d486b6688ecec Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1658 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Nico Huber
Stefan Reinauer
parent
252d39bb15
commit
a74af56dc1
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@ -1 +1 @@
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ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
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ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c speedstep.c
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@ -2,6 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2009 coresystems GmbH
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* 2012 secunet Security Networks AG
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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@ -28,7 +29,18 @@
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#include <cpu/intel/speedstep.h>
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#include <device/device.h>
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// XXX: PSS table values for power consumption are for Merom only
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/**
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* @brief Returns c-state entries for this system
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*
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* This function is usually overwritten in mainboard code.
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*
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* @return Number of c-states *entries will point to.
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*/
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int __attribute__((weak)) get_cst_entries(acpi_cstate_t **entries
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__attribute__((unused)))
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{
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return 0;
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}
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static int determine_total_number_of_cores(void)
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{
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@ -47,110 +59,133 @@ static int determine_total_number_of_cores(void)
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return count;
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}
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/**
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* @brief Returns three times the FSB clock in MHz
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*
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* The result of calculations with the returned value shall be divided by 3.
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* This helps to avoid rounding errors.
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*/
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static int get_fsb(void)
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{
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const u32 fsbcode = rdmsr(0xcd).lo & 7;
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switch (fsbcode) {
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case 0: return 266;
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case 1: return 133;
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case 2: return 200;
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case 3: return 166;
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case 4: return 333;
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case 5: return 100;
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case 6: return 400;
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case 0: return 800; /* / 3 == 266 */
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case 1: return 400; /* / 3 == 133 */
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case 2: return 600; /* / 3 == 200 */
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case 3: return 500; /* / 3 == 166 */
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case 4: return 1000; /* / 3 == 333 */
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case 5: return 300; /* / 3 == 100 */
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case 6: return 1200; /* / 3 == 400 */
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}
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printk(BIOS_DEBUG, "Warning: No supported FSB frequency. Assuming 200MHz\n");
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return 200;
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printk(BIOS_WARNING,
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"Warning: No supported FSB frequency. Assuming 200MHz\n");
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return 600;
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}
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int __attribute__((weak)) get_cst_entries(acpi_cstate_t **entries __attribute__((unused)))
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static int gen_pstate_entries(const sst_table_t *const pstates,
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const int cpuID, const int cores_per_package,
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const uint8_t coordination)
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{
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return 0;
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int i;
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int len, len_ps;
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int frequency;
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len = acpigen_write_empty_PCT();
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len += acpigen_write_PSD_package(
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cpuID, cores_per_package, coordination);
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len += acpigen_write_name("_PSS");
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const int fsb3 = get_fsb();
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const int min_ratio2 = SPEEDSTEP_DOUBLE_RATIO(
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pstates->states[pstates->num_states - 1]);
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const int max_ratio2 = SPEEDSTEP_DOUBLE_RATIO(pstates->states[0]);
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printk(BIOS_DEBUG, "clocks between %d and %d MHz.\n",
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(min_ratio2 * fsb3)
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/ (pstates->states[pstates->num_states - 1].is_slfm ? 12 : 6),
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(max_ratio2 * fsb3) / 6);
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printk(BIOS_DEBUG, "adding %x P-States between "
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"busratio %x and %x, ""incl. P0\n",
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pstates->num_states, min_ratio2 / 2, max_ratio2 / 2);
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len_ps = acpigen_write_package(pstates->num_states);
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for (i = 0; i < pstates->num_states; ++i) {
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const sst_state_t *const pstate = &pstates->states[i];
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/* Report frequency of turbo mode as that of HFM + 1. */
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if (pstate->is_turbo)
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frequency = (SPEEDSTEP_DOUBLE_RATIO(
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pstates->states[i + 1]) * fsb3) / 6 + 1;
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/* Super-LFM runs at half frequency. */
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else if (pstate->is_slfm)
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frequency = (SPEEDSTEP_DOUBLE_RATIO(*pstate)*fsb3)/12;
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else
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frequency = (SPEEDSTEP_DOUBLE_RATIO(*pstate)*fsb3)/6;
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len_ps += acpigen_write_PSS_package(
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frequency, pstate->power, 0, 0,
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SPEEDSTEP_ENCODE_STATE(*pstate),
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SPEEDSTEP_ENCODE_STATE(*pstate));
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}
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len_ps--;
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acpigen_patch_len(len_ps);
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len += acpigen_write_PPC(0);
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len += len_ps;
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return len;
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}
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/**
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* @brief Generate ACPI entries for Speedstep for each cpu
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*/
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void generate_cpu_entries(void)
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{
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int len_pr, len_ps;
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int len_pr;
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int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
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msr_t msr;
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int totalcores = determine_total_number_of_cores();
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int cores_per_package = (cpuid_ebx(1)>>16) & 0xff;
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int numcpus = totalcores/cores_per_package; // this assumes that all CPUs share the same layout
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int count;
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acpi_cstate_t *cst_entries;
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int numcpus = totalcores/cores_per_package; /* This assumes that all
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CPUs share the same
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layout. */
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int num_cstates;
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acpi_cstate_t *cstates;
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sst_table_t pstates;
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uint8_t coordination;
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printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package);
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printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
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numcpus, cores_per_package);
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for (cpuID=1; cpuID <=numcpus; cpuID++) {
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num_cstates = get_cst_entries(&cstates);
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speedstep_gen_pstates(&pstates);
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if (((cpuid_eax(1) >> 4) & 0xffff) == 0x1067)
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/* For Penryn use HW_ALL. */
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coordination = HW_ALL;
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else
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/* Use SW_ANY as that was the default. */
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coordination = SW_ANY;
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for (cpuID = 0; cpuID < numcpus; ++cpuID) {
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for (coreID=1; coreID<=cores_per_package; coreID++) {
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if (coreID>1) {
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pcontrol_blk = 0;
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plen = 0;
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}
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/* Generate processor \_PR.CPUx. */
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len_pr = acpigen_write_processor(
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(cpuID - 1) * cores_per_package + coreID - 1, pcontrol_blk, plen);
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len_pr += acpigen_write_empty_PCT();
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len_pr += acpigen_write_PSD_package(cpuID-1,cores_per_package,SW_ANY);
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if ((count = get_cst_entries(&cst_entries)) > 0)
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len_pr += acpigen_write_CST_package(cst_entries, count);
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len_pr += acpigen_write_name("_PSS");
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cpuID * cores_per_package + coreID - 1,
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pcontrol_blk, plen);
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int max_states=8;
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int busratio_step=2;
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msr = rdmsr(IA32_PERF_STS);
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int busratio_min=(msr.lo >> 24) & 0x1f;
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int busratio_max=(msr.hi >> (40-32)) & 0x1f;
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int vid_min=msr.lo & 0x3f;
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msr = rdmsr(IA32_PLATFORM_ID);
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int vid_max=msr.lo & 0x3f;
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int clock_max=get_fsb()*busratio_max;
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int clock_min=get_fsb()*busratio_min;
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printk(BIOS_DEBUG, "clocks between %d and %d MHz.\n", clock_min, clock_max);
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#define MEROM_MIN_POWER 16000
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#define MEROM_MAX_POWER 35000
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int power_max=MEROM_MAX_POWER;
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int power_min=MEROM_MIN_POWER;
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/* Generate p-state entries. */
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len_pr += gen_pstate_entries(&pstates, cpuID,
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cores_per_package, coordination);
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int num_states=(busratio_max-busratio_min)/busratio_step;
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while (num_states > max_states-1) {
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busratio_step <<= 1;
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num_states >>= 1;
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}
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printk(BIOS_DEBUG, "adding %x P-States between busratio %x and %x, incl. P0\n",
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num_states+1, busratio_min, busratio_max);
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int vid_step=(vid_max-vid_min)/num_states;
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int power_step=(power_max-power_min)/num_states;
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int clock_step=(clock_max-clock_min)/num_states;
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len_ps = acpigen_write_package(num_states + 1); /* For Super LFM, this must
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be increases by another one. */
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len_ps += acpigen_write_PSS_package(
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clock_max /*mhz*/, power_max /*mW*/, 0 /*lat1*/, 0 /*lat2*/,
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(busratio_max << 8) | vid_max /*control*/,
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(busratio_max << 8) | vid_max /*status*/);
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/* Generate c-state entries. */
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if (num_cstates > 0)
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len_pr += acpigen_write_CST_package(
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cstates, num_cstates);
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int current_busratio=busratio_min+((num_states-1)*busratio_step);
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int current_vid=vid_min+((num_states-1)*vid_step);
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int current_power=power_min+((num_states-1)*power_step);
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int current_clock=clock_min+((num_states-1)*clock_step);
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int i;
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for (i=0;i<num_states; i++) {
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len_ps += acpigen_write_PSS_package(
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current_clock /*mhz*/, current_power /*mW*/,
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0 /*lat1*/, 0 /*lat2*/,
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(current_busratio << 8) | current_vid /*control*/,
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(current_busratio << 8) | current_vid /*status*/);
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current_busratio -= busratio_step;
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current_vid -= vid_step;
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current_power -= power_step;
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current_clock -= clock_step;
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}
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len_ps--;
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acpigen_patch_len(len_ps);
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len_pr += acpigen_write_PPC(0);
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len_pr += len_ps;
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len_pr--;
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acpigen_patch_len(len_pr);
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}
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}
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}
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@ -0,0 +1,189 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 secunet Security Networks AG
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <types.h>
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#include <string.h>
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#include <arch/cpu.h>
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#include <cpu/x86/msr.h>
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#include <console/console.h>
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#include <cpu/intel/speedstep.h>
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/**
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* @brief Gather speedstep limits for current processor
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*
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* At least power limits are processor type specific. Penryn introduced half
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* steps in bus ratios. Don't know about Atom processors.
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*/
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static void speedstep_get_limits(sst_params_t *const params)
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{
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msr_t msr;
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const uint16_t cpu_id = (cpuid_eax(1) >> 4) & 0xffff;
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const uint32_t state_mask =
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/* Penryn supports non integer (i.e. half) ratios. */
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((cpu_id == 0x1067) ? SPEEDSTEP_RATIO_NONINT : 0)
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| SPEEDSTEP_RATIO_VALUE_MASK | SPEEDSTEP_VID_MASK;
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/* Initialize params to zero. */
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memset(params, '\0', sizeof(*params));
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/* Read Super-LFM parameters. */
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if (((rdmsr(MSR_EXTENDED_CONFIG).lo >> 27) & 3) == 3) {/*supported and
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enabled bits */
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msr = rdmsr(MSR_FSB_CLOCK_VCC);
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params->slfm = SPEEDSTEP_STATE_FROM_MSR(msr.lo, state_mask);
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params->slfm.dynfsb = 1;
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params->slfm.is_slfm = 1;
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}
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/* Read normal minimum parameters. */
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msr = rdmsr(MSR_THERM2_CTL);
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params->min = SPEEDSTEP_STATE_FROM_MSR(msr.lo, state_mask);
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/* Read normal maximum parameters. */
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/* Newer CPUs provide the normal maximum settings in
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IA32_PLATFORM_ID. The values in IA32_PERF_STS change
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when using turbo mode. */
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msr = rdmsr(IA32_PLATFORM_ID);
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params->max = SPEEDSTEP_STATE_FROM_MSR(msr.lo, state_mask);
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if (cpu_id == 0x006e) {
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/* Looks like Yonah CPUs don't have the frequency ratio in
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IA32_PLATFORM_ID. Use IA32_PERF_STS instead, the reading
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should be reliable as those CPUs don't have turbo mode. */
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msr = rdmsr(IA32_PERF_STS);
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params->max.ratio = (msr.hi & SPEEDSTEP_RATIO_VALUE_MASK)
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>> SPEEDSTEP_RATIO_SHIFT;
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}
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/* Read turbo parameters. */
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msr = rdmsr(MSR_FSB_CLOCK_VCC);
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if ((msr.hi & (1 << (63 - 32))) &&
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/* supported and */
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!(rdmsr(IA32_MISC_ENABLES).hi & (1 << (38 - 32)))) {
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/* not disabled */
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params->turbo = SPEEDSTEP_STATE_FROM_MSR(msr.hi, state_mask);
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params->turbo.is_turbo = 1;
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}
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/* Set power limits by processor type. */
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/* Defined values match the normal voltage versions only. But
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they are only a hint for OSPM, so this should not hurt much. */
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switch (cpu_id) {
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case 0x006e:
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/* Yonah */
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params->min.power = SPEEDSTEP_MIN_POWER_YONAH;
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params->max.power = SPEEDSTEP_MAX_POWER_YONAH;
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break;
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case 0x1067:
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/* Penryn */
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params->slfm.power = SPEEDSTEP_SLFM_POWER_PENRYN;
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params->min.power = SPEEDSTEP_MIN_POWER_PENRYN;
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params->max.power = SPEEDSTEP_MAX_POWER_PENRYN;
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params->turbo.power = SPEEDSTEP_MAX_POWER_PENRYN;
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break;
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case 0x006f:
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/* Merom */
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default:
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/* Use Merom values by default (as before). */
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params->slfm.power = SPEEDSTEP_SLFM_POWER_MEROM;
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params->min.power = SPEEDSTEP_MIN_POWER_MEROM;
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params->max.power = SPEEDSTEP_MAX_POWER_MEROM;
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params->turbo.power = SPEEDSTEP_MAX_POWER_MEROM;
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break;
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}
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}
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/**
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* @brief Generate full p-states table from processor parameters
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*
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* This is generic code and should work at least for Merom and Penryn
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* processors. It is used to generate acpi tables and configure EMTTM.
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*/
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void speedstep_gen_pstates(sst_table_t *const table)
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{
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sst_params_t params;
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/* Gather speedstep limits. */
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speedstep_get_limits(¶ms);
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/*\ First, find the number of normal states: \*/
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/* Calculate with doubled values to work
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around non-integer (.5) bus ratios. */
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const int power_diff2 = (params.max.power - params.min.power) * 2;
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const int vid_diff2 = (params.max.vid - params.min.vid) * 2;
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const int max_ratio2 = SPEEDSTEP_DOUBLE_RATIO(params.max);
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const int min_ratio2 = SPEEDSTEP_DOUBLE_RATIO(params.min);
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const int ratio_diff2 = max_ratio2 - min_ratio2;
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/* Calculate number of normal states (LFM to HFM, min to max). */
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/* Increase step size, until all states fit into the table.
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(Note: First try should always work, if
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SPEEDSTEP_MAX_NORMAL_STATES is set correctly.) */
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int states, step2 = 0;
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do {
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step2 += 2 * 2; /* Must be a multiple of 2 (doubled). */
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states = ratio_diff2 / step2 + 1;
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} while (states > SPEEDSTEP_MAX_NORMAL_STATES);
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if (step2 > 4)
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printk(BIOS_INFO, "Enhanced Speedstep processor with "
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"more than %d possible p-states.\n",
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SPEEDSTEP_MAX_NORMAL_STATES);
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if (states < 2) /* Report at least two normal states. */
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states = 2;
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/*\ Now, fill the table: \*/
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table->num_states = 0;
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/* Add turbo state if supported. */
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if (params.turbo.is_turbo)
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table->states[table->num_states++] = params.turbo;
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/* Add HFM first. */
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table->states[table->num_states] = params.max;
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/* Work around HFM and LFM having the same bus ratio. */
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if ((params.max.dynfsb == params.min.dynfsb) &&
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(params.max.nonint == params.min.nonint) &&
|
||||
(params.max.ratio == params.min.ratio))
|
||||
table->states[table->num_states].vid = params.min.vid;
|
||||
++table->num_states;
|
||||
--states;
|
||||
|
||||
/* Now, add all other normal states based on LFM (min). */
|
||||
const int power_step = (power_diff2 / states) / 2;
|
||||
const int vid_step = (vid_diff2 / states) / 2;
|
||||
const int ratio_step = step2 / 2;
|
||||
int power = params.min.power + (states - 1) * power_step;
|
||||
int vid = params.min.vid + (states - 1) * vid_step;
|
||||
int ratio = params.min.ratio + (states - 1) * ratio_step;
|
||||
for (; states > 0; --states) {
|
||||
table->states[table->num_states++] =
|
||||
(sst_state_t){ 0, 0, ratio, vid, 0, 0, power };
|
||||
power -= power_step;
|
||||
vid -= vid_step;
|
||||
ratio -= ratio_step;
|
||||
}
|
||||
|
||||
/* At last, add Super-LFM state if supported. */
|
||||
if (params.slfm.is_slfm)
|
||||
table->states[table->num_states++] = params.slfm;
|
||||
}
|
||||
|
|
@ -2,6 +2,7 @@
|
|||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* 2012 secunet Security Networks AG
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
|
|
@ -19,6 +20,11 @@
|
|||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef CPU_INTEL_SPEEDSTEP_H
|
||||
#define CPU_INTEL_SPEEDSTEP_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* Magic value used to locate speedstep configuration in the device tree */
|
||||
#define SPEEDSTEP_APIC_MAGIC 0xACAC
|
||||
|
||||
|
|
@ -39,3 +45,71 @@
|
|||
#define IA32_PERF_CTL 0x199
|
||||
#define MSR_THERM2_CTL 0x19D
|
||||
#define IA32_MISC_ENABLES 0x1A0
|
||||
#define MSR_FSB_CLOCK_VCC 0xce
|
||||
#define MSR_EXTENDED_CONFIG 0xee
|
||||
|
||||
|
||||
typedef struct {
|
||||
uint8_t dynfsb : 1; /* whether this is SLFM */
|
||||
uint8_t nonint : 1; /* add .5 to ratio */
|
||||
uint8_t ratio : 6;
|
||||
uint8_t vid;
|
||||
uint8_t is_turbo;
|
||||
uint8_t is_slfm;
|
||||
uint32_t power;
|
||||
} sst_state_t;
|
||||
#define SPEEDSTEP_RATIO_SHIFT 8
|
||||
#define SPEEDSTEP_RATIO_DYNFSB_SHIFT (7 + SPEEDSTEP_RATIO_SHIFT)
|
||||
#define SPEEDSTEP_RATIO_DYNFSB (1 << SPEEDSTEP_RATIO_DYNFSB_SHIFT)
|
||||
#define SPEEDSTEP_RATIO_NONINT_SHIFT (6 + SPEEDSTEP_RATIO_SHIFT)
|
||||
#define SPEEDSTEP_RATIO_NONINT (1 << SPEEDSTEP_RATIO_NONINT_SHIFT)
|
||||
#define SPEEDSTEP_RATIO_VALUE_MASK (0x1f << SPEEDSTEP_RATIO_SHIFT)
|
||||
#define SPEEDSTEP_VID_MASK 0x3f
|
||||
#define SPEEDSTEP_STATE_FROM_MSR(val, mask) ((sst_state_t){ \
|
||||
0, /* dynfsb won't be read. */ \
|
||||
((val & mask) & SPEEDSTEP_RATIO_NONINT) ? 1 : 0, \
|
||||
(((val & mask) & SPEEDSTEP_RATIO_VALUE_MASK) \
|
||||
>> SPEEDSTEP_RATIO_SHIFT), \
|
||||
(val & mask) & SPEEDSTEP_VID_MASK, \
|
||||
0, /* not turbo by default */ \
|
||||
0, /* not slfm by default */ \
|
||||
0 /* power is hardcoded in software. */ \
|
||||
})
|
||||
#define SPEEDSTEP_ENCODE_STATE(state) ( \
|
||||
((uint16_t)(state).dynfsb << SPEEDSTEP_RATIO_DYNFSB_SHIFT) | \
|
||||
((uint16_t)(state).nonint << SPEEDSTEP_RATIO_NONINT_SHIFT) | \
|
||||
((uint16_t)(state).ratio << SPEEDSTEP_RATIO_SHIFT) | \
|
||||
((uint16_t)(state).vid & SPEEDSTEP_VID_MASK))
|
||||
#define SPEEDSTEP_DOUBLE_RATIO(state) ( \
|
||||
((uint8_t)(state).ratio * 2) + (state).nonint)
|
||||
|
||||
typedef struct {
|
||||
sst_state_t slfm;
|
||||
sst_state_t min;
|
||||
sst_state_t max;
|
||||
sst_state_t turbo;
|
||||
} sst_params_t;
|
||||
|
||||
/* Looking at core2's spec, the highest normal bus ratio for an eist enabled
|
||||
processor is 14, the lowest is always 6. This makes 5 states with the
|
||||
minimal step width of 2. With turbo mode and super LFM we have at most 7. */
|
||||
#define SPEEDSTEP_MAX_NORMAL_STATES 5
|
||||
#define SPEEDSTEP_MAX_STATES (SPEEDSTEP_MAX_NORMAL_STATES + 2)
|
||||
typedef struct {
|
||||
/* Table of p-states for EMTTM and ACPI by decreasing performance. */
|
||||
sst_state_t states[SPEEDSTEP_MAX_STATES];
|
||||
int num_states;
|
||||
} sst_table_t;
|
||||
|
||||
void speedstep_gen_pstates(sst_table_t *);
|
||||
|
||||
#define SPEEDSTEP_MAX_POWER_YONAH 31000
|
||||
#define SPEEDSTEP_MIN_POWER_YONAH 13100
|
||||
#define SPEEDSTEP_MAX_POWER_MEROM 35000
|
||||
#define SPEEDSTEP_MIN_POWER_MEROM 25000
|
||||
#define SPEEDSTEP_SLFM_POWER_MEROM 12000
|
||||
#define SPEEDSTEP_MAX_POWER_PENRYN 35000
|
||||
#define SPEEDSTEP_MIN_POWER_PENRYN 15000
|
||||
#define SPEEDSTEP_SLFM_POWER_PENRYN 12000
|
||||
|
||||
#endif /* CPU_INTEL_SPEEDSTEP_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue