fix up config space.

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2367 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich 2006-08-08 18:02:12 +00:00
parent 90e68aef68
commit a758acab7f
1 changed files with 5 additions and 6 deletions

View File

@ -3,7 +3,7 @@
* *
*/ */
static void setup_s2895_resource_map(void) static void setup_ultra40_resource_map(void)
{ {
static const unsigned int register_values[] = { static const unsigned int register_values[] = {
/* Careful set limit registers before base registers which contain the enables */ /* Careful set limit registers before base registers which contain the enables */
@ -253,11 +253,10 @@ static void setup_s2895_resource_map(void)
* [31:24] Bus Number Limit i * [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i * This field defines the highest bus number in configuration region i
*/ */
PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000, 0x7f000103,
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000, 0xff800113,
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0xff800013, PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xec), 0x0000, 0x00000000,
}; };
int max; int max;