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intel core and core 2: 

- small preprocessor fix
- leave some space in the CAR area for the usbdebug structure
  if usbdebug is used

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4859 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2009-10-26 16:49:16 +00:00 committed by Stefan Reinauer
parent fbb8a01543
commit a769344d43
2 changed files with 14 additions and 4 deletions
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9
src/cpu/intel/model_6ex/cache_as_ram.inc
View File

@ -94,7 +94,6 @@ clear_mtrrs:
//movl $0x23322332, %eax
xorl %eax, %eax
rep stosl
#endif
/* Enable Cache As RAM mode by disabling cache */
movl %cr0, %eax
@ -117,10 +116,16 @@ clear_mtrrs:
/* enable cache */
movl %cr0, %eax
andl $( ~( (1 << 30) | (1 << 29) ) ), %eax
movl %eax, %cr0
movl %eax, %cr0
#endif
/* Set up stack pointer */
#if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1)
/* leave some space for the struct ehci_debug_info */
movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
#else
movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
#endif
movl %eax, %esp
/* Restore the BIST result */

9
src/cpu/intel/model_6fx/cache_as_ram.inc
View File

@ -101,7 +101,6 @@ clear_mtrrs:
//movl $0x23322332, %eax
xorl %eax, %eax
rep stosl
#endif
/* Enable Cache As RAM mode by disabling cache */
movl %cr0, %eax
@ -124,10 +123,16 @@ clear_mtrrs:
/* enable cache */
movl %cr0, %eax
andl $( ~( (1 << 30) | (1 << 29) ) ), %eax
movl %eax, %cr0
movl %eax, %cr0
#endif
/* Set up stack pointer */
#if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1)
/* leave some space for the struct ehci_debug_info */
movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
#else
movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
#endif
movl %eax, %esp
/* Restore the BIST result */