From a76e64709491664765e33b55826e5af87c1f20ce Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Fri, 23 Jul 2021 14:53:05 -0600 Subject: [PATCH] soc/amd/common/block/cpu: Remove magic number in memlayout The SPI DMA controller can only perform transactions on a cache line boundary. This change removes the magic number and uses the #define to make it clear. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel Change-Id: Ie7b851dc2433e44a23224c3ff733fdea5fbcca0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58377 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld index 59631f3ada..005bde093b 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld @@ -103,8 +103,8 @@ SECTIONS * the payload on non-S3 boots, so we don't need to reserve it from the * OS. The 64 byte alignment is required by the SPI DMA controller. */ - . = ALIGN(64); - REGION(payload_preload_cache, ., CONFIG_PAYLOAD_PRELOAD_CACHE_SIZE, 64) + . = ALIGN(ARCH_CACHELINE_ALIGN_SIZE); + REGION(payload_preload_cache, ., CONFIG_PAYLOAD_PRELOAD_CACHE_SIZE, ARCH_CACHELINE_ALIGN_SIZE) #endif RAMSTAGE(CONFIG_RAMBASE, 8M)