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soc/rockchip/rk3399/sdram: Order and group tsel variables 

Order and group tsel variables in a meaningful way.

No functional changes.

Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I417e0fbc129c2d9ad1b345bcff2e25ca6eca83bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50866
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Moritz Fischer 2021-02-17 14:25:25 -08:00 committed by ron minnich
parent c4ca8c3556
commit a76f659840
1 changed files with 21 additions and 15 deletions
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36
src/soc/rockchip/rk3399/sdram.c
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@ -182,34 +182,40 @@ static void set_ds_odt(u32 channel, const struct rk3399_sdram_params *params)
if (params->dramtype == LPDDR4) { if (params->dramtype == LPDDR4) {
tsel_rd_select_p = PHY_DRV_ODT_Hi_Z; tsel_rd_select_p = PHY_DRV_ODT_Hi_Z;
tsel_wr_select_p = PHY_DRV_ODT_40;
ca_tsel_wr_select_p = PHY_DRV_ODT_40;
tsel_idle_select_p = PHY_DRV_ODT_Hi_Z;
tsel_rd_select_n = PHY_DRV_ODT_240; tsel_rd_select_n = PHY_DRV_ODT_240;
tsel_wr_select_p = PHY_DRV_ODT_40;
tsel_wr_select_n = PHY_DRV_ODT_40; tsel_wr_select_n = PHY_DRV_ODT_40;
ca_tsel_wr_select_n = PHY_DRV_ODT_40;
tsel_idle_select_p = PHY_DRV_ODT_Hi_Z;
tsel_idle_select_n = PHY_DRV_ODT_240; tsel_idle_select_n = PHY_DRV_ODT_240;
ca_tsel_wr_select_p = PHY_DRV_ODT_40;
ca_tsel_wr_select_n = PHY_DRV_ODT_40;
} else if (params->dramtype == LPDDR3) { } else if (params->dramtype == LPDDR3) {
tsel_rd_select_p = PHY_DRV_ODT_240; tsel_rd_select_p = PHY_DRV_ODT_240;
tsel_wr_select_p = PHY_DRV_ODT_34_3;
ca_tsel_wr_select_p = PHY_DRV_ODT_48;
tsel_idle_select_p = PHY_DRV_ODT_240;
tsel_rd_select_n = PHY_DRV_ODT_Hi_Z; tsel_rd_select_n = PHY_DRV_ODT_Hi_Z;
tsel_wr_select_p = PHY_DRV_ODT_34_3;
tsel_wr_select_n = PHY_DRV_ODT_34_3; tsel_wr_select_n = PHY_DRV_ODT_34_3;
ca_tsel_wr_select_n = PHY_DRV_ODT_48;
tsel_idle_select_p = PHY_DRV_ODT_240;
tsel_idle_select_n = PHY_DRV_ODT_Hi_Z; tsel_idle_select_n = PHY_DRV_ODT_Hi_Z;
ca_tsel_wr_select_p = PHY_DRV_ODT_48;
ca_tsel_wr_select_n = PHY_DRV_ODT_48;
} else { } else {
tsel_rd_select_p = PHY_DRV_ODT_240; tsel_rd_select_p = PHY_DRV_ODT_240;
tsel_wr_select_p = PHY_DRV_ODT_34_3;
ca_tsel_wr_select_p = PHY_DRV_ODT_34_3;
tsel_idle_select_p = PHY_DRV_ODT_240;
tsel_rd_select_n = PHY_DRV_ODT_240; tsel_rd_select_n = PHY_DRV_ODT_240;
tsel_wr_select_p = PHY_DRV_ODT_34_3;
tsel_wr_select_n = PHY_DRV_ODT_34_3; tsel_wr_select_n = PHY_DRV_ODT_34_3;
ca_tsel_wr_select_n = PHY_DRV_ODT_34_3;
tsel_idle_select_p = PHY_DRV_ODT_240;
tsel_idle_select_n = PHY_DRV_ODT_240; tsel_idle_select_n = PHY_DRV_ODT_240;
ca_tsel_wr_select_p = PHY_DRV_ODT_34_3;
ca_tsel_wr_select_n = PHY_DRV_ODT_34_3;
} }
if (params->odt == 1) if (params->odt == 1)