mb/google/volteer/variants/copano: Add gpio-keys ACPI node for PENH

Use gpio_keys driver to add ACPI node for pen eject event.
Also setting gpio wake pin for wake events.

BUG=b:175519097
BRANCH=firmware-volteer-13672.B
TEST=build and verify on a Copano

Change-Id: Id0a132aa398abde4983af123d00e355ac61839a8
Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51249
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
hao_chou 2021-03-04 17:44:06 +08:00 committed by Patrick Georgi
parent 7f61e5703b
commit a776ebb801
2 changed files with 14 additions and 1 deletions

View File

@ -111,7 +111,7 @@ static const struct pad_config override_gpio_table[] = {
/* E16 : ISH_GP7 ==> USB_A0_RT_RST_ODL */
PAD_CFG_GPO(GPP_E16, 1, DEEP),
/* E17 : THC0_SPI1_INT# ==> PEN_DET_ODL */
PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE),
PAD_CFG_GPI_GPIO_DRIVER(GPP_E17, NONE, PLTRST),
/* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */
PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF4),

View File

@ -94,6 +94,19 @@ chip soc/intel/tigerlake
register "hid_desc_reg_offset" = "0x01"
device i2c 10 on end
end
chip drivers/generic/gpio_keys
register "name" = ""PENH""
# GPP_E17 is the IRQ source, and GPP_E1 is the wake source
register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_E17)"
register "key.wake_gpe" = "GPE0_DW2_01"
register "key.wakeup_route" = "WAKEUP_ROUTE_SCI"
register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
register "key.dev_name" = ""EJCT""
register "key.linux_code" = "SW_PEN_INSERTED"
register "key.linux_input_type" = "EV_SW"
register "key.label" = ""pen_eject""
device generic 0 on end
end
end
device ref i2c5 on
chip drivers/i2c/generic