mb/google/volteer/variants/copano: Add gpio-keys ACPI node for PENH
Use gpio_keys driver to add ACPI node for pen eject event. Also setting gpio wake pin for wake events. BUG=b:175519097 BRANCH=firmware-volteer-13672.B TEST=build and verify on a Copano Change-Id: Id0a132aa398abde4983af123d00e355ac61839a8 Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51249 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -111,7 +111,7 @@ static const struct pad_config override_gpio_table[] = {
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/* E16 : ISH_GP7 ==> USB_A0_RT_RST_ODL */
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/* E16 : ISH_GP7 ==> USB_A0_RT_RST_ODL */
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PAD_CFG_GPO(GPP_E16, 1, DEEP),
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PAD_CFG_GPO(GPP_E16, 1, DEEP),
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/* E17 : THC0_SPI1_INT# ==> PEN_DET_ODL */
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/* E17 : THC0_SPI1_INT# ==> PEN_DET_ODL */
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PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE),
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PAD_CFG_GPI_GPIO_DRIVER(GPP_E17, NONE, PLTRST),
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/* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */
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/* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */
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PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF4),
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PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF4),
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@ -94,6 +94,19 @@ chip soc/intel/tigerlake
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register "hid_desc_reg_offset" = "0x01"
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register "hid_desc_reg_offset" = "0x01"
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device i2c 10 on end
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device i2c 10 on end
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end
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end
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chip drivers/generic/gpio_keys
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register "name" = ""PENH""
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# GPP_E17 is the IRQ source, and GPP_E1 is the wake source
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register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_E17)"
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register "key.wake_gpe" = "GPE0_DW2_01"
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register "key.wakeup_route" = "WAKEUP_ROUTE_SCI"
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register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
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register "key.dev_name" = ""EJCT""
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register "key.linux_code" = "SW_PEN_INSERTED"
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register "key.linux_input_type" = "EV_SW"
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register "key.label" = ""pen_eject""
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device generic 0 on end
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end
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end
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end
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device ref i2c5 on
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device ref i2c5 on
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chip drivers/i2c/generic
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chip drivers/i2c/generic
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