From a78ab4b0af72240fa4dba5a520c635d44b97eff2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sat, 2 Oct 2021 17:46:45 +0200 Subject: [PATCH] soc/intel/dnv_ns: correct size of GPE0 registers in FADT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are 4 GPE0 STS/EN register pairs, each 32 bit wide. However, SoC code sets a GPE0 block size of 4 byte length instead of 32 byte. The resulting value of `x_gpe0_blk.bit_with` is wrong, too (32 bit instead of 256 bit). Drop the overrides and let common ACPI code set the correct values based on `GPE0_REG_MAX`. Change-Id: I45ee0f6678784c292ee3ed3446bf3c0f2d53b633 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/58086 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/soc/intel/denverton_ns/acpi.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index aa59aa8c81..574d106fa0 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -101,7 +101,6 @@ void soc_fill_fadt(acpi_fadt_t *fadt) /* Control Registers - Length */ fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 8; fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; @@ -149,14 +148,6 @@ void soc_fill_fadt(acpi_fadt_t *fadt) fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; fadt->x_pm_tmr_blk.addrh = 0x00; - - /* General-Purpose Event Registers */ - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0x00; } static acpi_tstate_t denverton_tss_table[] = {