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superio/ite/common/early_serial.c: ite_kill_watchdog: set timeout to 0 

Set the watchdog timeout to 0 in ite_kill_watchdog, as in some ITE
models it is set to non-zero by default, activating the watchdog despite
us setting the control register to 0.

Based on:
- "ITE IT8786E-I Preliminary Specification V0.4.1 (For D Version)"
- Linux it87_wdt driver

Change-Id: I1e78e2acc96e9dd0f283c5c674d3277d26cdee26
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Michał Kopeć 2022-07-26 13:10:36 +02:00 committed by Martin L Roth
parent 0700940bb7
commit a7a40a5b10
1 changed files with 10 additions and 6 deletions
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16
src/superio/ite/common/early_serial.c
View File

@ -7,12 +7,14 @@
#include "ite.h"
/* Global configuration registers. */
#define ITE_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
#define ITE_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
#define ITE_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
#define ITE_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
#define ITE_CONFIG_REG_MFC 0x2a /* multi function pin */
#define ITE_CONFIG_REG_WATCHDOG 0x72 /* watchdog config */
#define ITE_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
#define ITE_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
#define ITE_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
#define ITE_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
#define ITE_CONFIG_REG_MFC 0x2a /* multi function pin */
#define ITE_CONFIG_REG_WATCHDOG 0x72 /* watchdog config */
#define ITE_CONFIG_REG_WDT_TIMEOUT_LSB 0x73 /* watchdog timeout (LSB) */
#define ITE_CONFIG_REG_WDT_TIMEOUT_MSB 0x74 /* watchdog timeout (MSB) */
/* Helper procedure */
static void ite_sio_write(pnp_devfn_t dev, u8 reg, u8 value)
@ -130,5 +132,7 @@ void ite_kill_watchdog(pnp_devfn_t dev)
{
pnp_enter_conf_state(dev);
ite_sio_write(dev, ITE_CONFIG_REG_WATCHDOG, 0x00);
ite_sio_write(dev, ITE_CONFIG_REG_WDT_TIMEOUT_LSB, 0x00);
ite_sio_write(dev, ITE_CONFIG_REG_WDT_TIMEOUT_MSB, 0x00);
pnp_exit_conf_state(dev);
}