skylake: do not overlap resources

FSP was setting up the TCO registers to be mapped at 0x400.
However, the SMBus initialization in romstage was mapping
its I/O BAR to 0x400 as well. The result seemed to cause the
TCO register to be hidden. However, the board was rebooting in
depthcharge when the SMBus device was enabled from a TCO timeout.
As the TCO timer was halted before the double resource assignment
it's not clear how the TCO was getting re-enabled. In either case,
the current behavior is wrong.

BUG=chrome-os-partner:42407
BRANCH=None
TEST=Built and booted glados w/ SMBus enabled.

Original-Change-Id: I43c0d67a76abac51ccfd5105245792981fbcd04c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290363
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: I3839290768c27626c3fd2d67d5de94c291c1386e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11180
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/soc/intel/skylake/include/soc/iomap.h

@@ -21,6 +21,9 @@
 #ifndef _SOC_IOMAP_H_
 #define _SOC_IOMAP_H_
 
+/*
+ * Memory-mapped I/O registers.
+ */
 #define MCFG_BASE_ADDRESS	CONFIG_MMCONF_BASE_ADDRESS
 #define MCFG_BASE_SIZE		0x4000000
 
@@ -54,13 +57,20 @@
 #define PCH_PWRM_BASE_ADDRESS	0xfe000000
 #define PCH_PWRM_BASE_SIZE	0x10000
 
+/*
+ * I/O port address space
+ */
+#define SMBUS_BASE_ADDRESS	0x0efa0
+#define SMBUS_BASE_SIZE		0x20
+
 #define ACPI_BASE_ADDRESS	0x1800
 #define ACPI_BASE_SIZE		0x100
 
+/* FIXME: not applicable as there is no I/O space for gpio access. */
 #define GPIO_BASE_ADDRESS	0x1400
 #define GPIO_BASE_SIZE		0x400
 
-#define SMBUS_BASE_ADDRESS	0x0400
-#define SMBUS_BASE_SIZE		0x10
+#define TCO_BASE_ADDDRESS	0x400
+#define TCO_BASE_SIZE		0x20
 
 #endif