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soc/intel/tigerlake: Check TBT & TCSS ports for wake events 

Wakes from TBT ports and TCSS devices will show up as PME_B0_STS wakes,
so add checks for wakes from these devices in
pch_log_pme_internal_wake_source.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie9904c3c01ea85fcd83218fcfeaa4378b07c1463
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47396
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Wawrzynczak 2020-11-10 09:57:19 -07:00
parent 56fcfb5b4f
commit a7b60e7dc8
1 changed files with 31 additions and 6 deletions
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37
src/soc/intel/tigerlake/elog.c
View File

@ -60,12 +60,13 @@ static void pch_log_rp_wake_source(void)
static void pch_log_pme_internal_wake_source(void) static void pch_log_pme_internal_wake_source(void)
{ {
const struct pme_map ipme_map[] = { const struct pme_map ipme_map[] = {
{ PCH_DEVFN_HDA, ELOG_WAKE_SOURCE_PME_HDA }, { PCH_DEVFN_HDA, ELOG_WAKE_SOURCE_PME_HDA },
{ PCH_DEVFN_GBE, ELOG_WAKE_SOURCE_PME_GBE }, { PCH_DEVFN_GBE, ELOG_WAKE_SOURCE_PME_GBE },
{ PCH_DEVFN_SATA, ELOG_WAKE_SOURCE_PME_SATA }, { PCH_DEVFN_SATA, ELOG_WAKE_SOURCE_PME_SATA },
{ PCH_DEVFN_CSE, ELOG_WAKE_SOURCE_PME_CSE }, { PCH_DEVFN_CSE, ELOG_WAKE_SOURCE_PME_CSE },
{ PCH_DEVFN_USBOTG, ELOG_WAKE_SOURCE_PME_XDCI }, { PCH_DEVFN_USBOTG, ELOG_WAKE_SOURCE_PME_XDCI },
{ PCH_DEVFN_CNVI_WIFI, ELOG_WAKE_SOURCE_PME_WIFI }, { PCH_DEVFN_CNVI_WIFI, ELOG_WAKE_SOURCE_PME_WIFI },
{ SA_DEVFN_TCSS_XDCI, ELOG_WAKE_SOURCE_PME_TCSS_XDCI },
}; };
const struct xhci_wake_info xhci_wake_info[] = { const struct xhci_wake_info xhci_wake_info[] = {
{ PCH_DEVFN_XHCI, ELOG_WAKE_SOURCE_PME_XHCI }, { PCH_DEVFN_XHCI, ELOG_WAKE_SOURCE_PME_XHCI },
@ -86,6 +87,30 @@ static void pch_log_pme_internal_wake_source(void)
} }
} }
/* Check Thunderbolt ports */
for (i = 0; i < NUM_TBT_FUNCTIONS; i++) {
const struct device *dev = pcidev_path_on_root(SA_DEVFN_TBT(i));
if (!dev)
continue;
if (pci_dev_is_wake_source(dev)) {
elog_add_event_wake(ELOG_WAKE_SOURCE_PME_TBT, i);
dev_found = true;
}
}
/* Check DMA devices */
for (i = 0; i < NUM_TCSS_DMA_FUNCTIONS; i++) {
const struct device *dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA(i));
if (!dev)
continue;
if (pci_dev_is_wake_source(dev)) {
elog_add_event_wake(ELOG_WAKE_SOURCE_PME_TCSS_DMA, i);
dev_found = true;
}
}
/* /*
* Check the XHCI controllers' USB2 & USB3 ports for wake events. There * Check the XHCI controllers' USB2 & USB3 ports for wake events. There
* are cases (GSMI logging for S0ix clears PME_STS_BIT) where the XHCI * are cases (GSMI logging for S0ix clears PME_STS_BIT) where the XHCI