From a7b922fd74d754f07d95dd6bdf5afc5284b08b5f Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 24 Jan 2023 01:00:08 +0100 Subject: [PATCH] soc/amd/common/block/include/acpi: drop MMIO_ACPI_CPU_CONTROL define This register isn't used in coreboot and isn't defined in the Picasso PPR #55570 Rev 3.18. To enter a lower C-state, a read request to a special IO port is done. The base address of this group of IO ports is configured in set_cstate_io_addr via the MSR_CSTATE_ADDRESS and that read won't leave the CPU. IIRC trying to put the MMIO mapping for entering the lower C-states into the _CST package didn't work as expected when it was tried on I think Cezanne. Signed-off-by: Felix Held Change-Id: Ib189993879feaa0a22f6810c4bd5c1a0bc8c5a27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72497 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/common/block/include/amdblocks/acpi.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h index 3dd8418411..9ffcb7e746 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpi.h +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -15,7 +15,6 @@ /* sleep types defined in include/acpi/acpi.h */ #define ACPI_PM1_CNT_SCIEN BIT(0) #define MMIO_ACPI_PM_TMR_BLK 0x08 -#define MMIO_ACPI_CPU_CONTROL 0x0c #define MMIO_ACPI_GPE0_BLK 0x14 #define MMIO_ACPI_GPE0_STS 0x14 #define MMIO_ACPI_GPE0_EN 0x18