mb/google/reef: do UART pad configuration at board-level

UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.

Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).

Change-Id: I279956f30cbb6fb031cdfe6aaa09b644b6b7d3e7
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49427
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/reef/bootblock.c

@@ -6,12 +6,16 @@
 #include <soc/gpio.h>
 #include <variant/ec.h>
 
-void bootblock_mainboard_init(void)
+void bootblock_mainboard_early_init(void)
 {
 	const struct pad_config *pads;
 	size_t num;
 
 	pads = variant_early_gpio_table(&num);
 	gpio_configure_pads(pads, num);
+}
+
+void bootblock_mainboard_init(void)
+{
 	mainboard_ec_init();
 }

src/mainboard/google/reef/variants/baseboard/gpio.c

@@ -354,6 +354,10 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), /* LPC_CLKRUN_N */
 	PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), /* LPC_FRAME_N */
 
+	/* UART */
+	PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1),	 /* LPSS_UART2_RXD */
+	PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* LPSS_UART2_TXD */
+
 	PAD_CFG_GPI(GPIO_75, UP_20K, DEEP),	 /* I2S1_BCLK -- PCH_WP */
 
 	/* I2C2 - TPM  */

src/mainboard/google/reef/variants/coral/gpio.c

@@ -355,6 +355,10 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), /* LPC_CLKRUN_N */
 	PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), /* LPC_FRAME_N */
 
+	/* UART */
+	PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1),	 /* LPSS_UART2_RXD */
+	PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* LPSS_UART2_TXD */
+
 	PAD_CFG_GPI(GPIO_75, UP_20K, DEEP),	 /* I2S1_BCLK -- PCH_WP */
 
 	/* I2C2 - TPM  */