mb/google/brya: Enable HECI1 communication

The patch enables HECI1 interface to allow OS applications to communicate
with CSE.

TEST=Verify PCI device 0:16.0 exposed in the lspci output

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I73acdd99788f9b60b7bcea372145e9694a124174
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54210
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/brya/variants/baseboard/devicetree.cb

@@ -25,6 +25,9 @@ chip soc/intel/alderlake
 		.tdp_pl2_override = 55,
 	}"
 
+	# Enable heci communication
+	register "HeciEnabled" = "1"
+
 	# This disabled autonomous GPIO power management, otherwise
 	# old cr50 FW only supports short pulses; need to clarify
 	# the minimum PCH IRQ pulse width with Intel, b/180111628