GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

intel/car: Use common TS_START_ROMSTAGE 

This timestamp also got unintentionally removed from some
boards as they were transformed to use common romstage entry.

Change-Id: I12be278a674f9a2ea073b170a223c41c7fc01a94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34970
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2019-08-18 06:55:52 +03:00
parent 8418fd418c
commit a7d2f29823
5 changed files with 2 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/cpu/intel/car/romstage.c
View File

@ -87,6 +87,8 @@ asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
asmlinkage void car_stage_entry(void) asmlinkage void car_stage_entry(void)
{ {
timestamp_add_now(TS_START_ROMSTAGE);
/* Assumes the hardware was set up during the bootblock */ /* Assumes the hardware was set up during the bootblock */
console_init(); console_init();

3
src/soc/intel/apollolake/romstage.c
View File

@ -47,7 +47,6 @@
#include <soc/systemagent.h> #include <soc/systemagent.h>
#include <spi_flash.h> #include <spi_flash.h>
#include <timer.h> #include <timer.h>
#include <timestamp.h>
#include "chip.h" #include "chip.h"
static const uint8_t hob_variable_guid[16] = { static const uint8_t hob_variable_guid[16] = {
@ -199,8 +198,6 @@ void mainboard_romstage_entry(void)
struct chipset_power_state *ps = pmc_get_power_state(); struct chipset_power_state *ps = pmc_get_power_state();
const void *new_var_data; const void *new_var_data;
timestamp_add_now(TS_START_ROMSTAGE);
soc_early_romstage_init(); soc_early_romstage_init();
s3wake = pmc_fill_power_state(ps) == ACPI_S3; s3wake = pmc_fill_power_state(ps) == ACPI_S3;

2
src/soc/intel/cannonlake/romstage/romstage.c
View File

@ -28,7 +28,6 @@
#include <soc/pm.h> #include <soc/pm.h>
#include <soc/romstage.h> #include <soc/romstage.h>
#include <string.h> #include <string.h>
#include <timestamp.h>
#include "../chip.h" #include "../chip.h"
@ -137,7 +136,6 @@ void mainboard_romstage_entry(void)
/* initialize Heci interface */ /* initialize Heci interface */
heci_init(HECI1_BASE_ADDRESS); heci_init(HECI1_BASE_ADDRESS);
timestamp_add_now(TS_START_ROMSTAGE);
s3wake = pmc_fill_power_state(ps) == ACPI_S3; s3wake = pmc_fill_power_state(ps) == ACPI_S3;
fsp_memory_init(s3wake); fsp_memory_init(s3wake);
pmc_set_disb(); pmc_set_disb();

2
src/soc/intel/icelake/romstage/romstage.c
View File

@ -29,7 +29,6 @@
#include <soc/romstage.h> #include <soc/romstage.h>
#include <soc/soc_chip.h> #include <soc/soc_chip.h>
#include <string.h> #include <string.h>
#include <timestamp.h>
#define FSP_SMBIOS_MEMORY_INFO_GUID \ #define FSP_SMBIOS_MEMORY_INFO_GUID \
{ \ { \
@ -121,7 +120,6 @@ void mainboard_romstage_entry(void)
/* initialize Heci interface */ /* initialize Heci interface */
heci_init(HECI1_BASE_ADDRESS); heci_init(HECI1_BASE_ADDRESS);
timestamp_add_now(TS_START_ROMSTAGE);
s3wake = pmc_fill_power_state(ps) == ACPI_S3; s3wake = pmc_fill_power_state(ps) == ACPI_S3;
fsp_memory_init(s3wake); fsp_memory_init(s3wake);
pmc_set_disb(); pmc_set_disb();

2
src/soc/intel/skylake/romstage/romstage_fsp20.c
View File

@ -32,7 +32,6 @@
#include <soc/pm.h> #include <soc/pm.h>
#include <soc/romstage.h> #include <soc/romstage.h>
#include <string.h> #include <string.h>
#include <timestamp.h>
#include <security/vboot/vboot_common.h> #include <security/vboot/vboot_common.h>
#include "../chip.h" #include "../chip.h"
@ -148,7 +147,6 @@ void mainboard_romstage_entry(void)
systemagent_early_init(); systemagent_early_init();
ps = pmc_get_power_state(); ps = pmc_get_power_state();
timestamp_add_now(TS_START_ROMSTAGE);
s3wake = pmc_fill_power_state(ps) == ACPI_S3; s3wake = pmc_fill_power_state(ps) == ACPI_S3;
fsp_memory_init(s3wake); fsp_memory_init(s3wake);
pmc_set_disb(); pmc_set_disb();