broadwell: Read and save HSIO version from ME in romstage

This can be used to know if HSIO registers need updating in ramstage
but it is not possible to query the ME for HSIO version after sending
the DRAM-init-done message.

BUG=chrome-os-partner:28234
BRANCH=samus
TEST=build and boot on samus, check for HSIO version messages in log

Original-Change-Id: Id6beeaf57287e8826b9f142f768636a9c055d7eb
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214259
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 637cbf5c1a1d922dab3f8a5cd4b3cd05617d1b92)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I29ce907804e892afde5f91e0b21688a50217cf13
Reviewed-on: http://review.coreboot.org/8966
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>

src/soc/intel/broadwell/broadwell/me.h

@@ -98,6 +98,10 @@ struct me_uma {
 #define  ME_INIT_STATUS_ERROR	2
 #define  ME_INIT_STATUS_SUCCESS_OTHER 3 /* SEE ME9 BWG */
 
+#define ME_HSIO_MESSAGE		(7 << 28)
+#define ME_HSIO_CMD_GETHSIOVER	1
+#define ME_HSIO_CMD_CLOSE	0
+
 struct me_did {
 	u32 uma_base: 16;
 	u32 reserved: 7;
@@ -197,6 +201,8 @@ struct me_hfs2 {
 	u32 progress_code: 4;
 } __attribute__ ((packed));
 
+#define PCI_ME_HFS5		0x68
+
 #define PCI_ME_H_GS2		0x70
 #define   PCI_ME_MBP_GIVE_UP	0x01
 
@@ -490,6 +496,7 @@ struct me_fwcaps {
 } __attribute__ ((packed));
 
 void intel_me_finalize(void);
+void intel_me_hsio_version(uint16_t *version, uint16_t *checksum);
 
 #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG)
 /* Defined in me_status.c for both romstage and ramstage */

src/soc/intel/broadwell/broadwell/pm.h

@@ -131,6 +131,8 @@ struct chipset_power_state {
 	uint16_t gen_pmcon2;
 	uint16_t gen_pmcon3;
 	int prev_sleep_state;
+	uint16_t hsio_version;
+	uint16_t hsio_checksum;
 };
 
 /* PM1_CNT */

src/soc/intel/broadwell/me_status.c

@@ -25,6 +25,7 @@
 #include <string.h>
 #include <broadwell/pci_devs.h>
 #include <broadwell/me.h>
+#include <delay.h>
 
 #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG)
 
@@ -279,3 +280,38 @@ void intel_me_status(void)
 	printk(BIOS_DEBUG, "\n");
 }
 #endif
+
+void intel_me_hsio_version(uint16_t *version, uint16_t *checksum)
+{
+	int count;
+	u32 hsiover;
+	struct me_hfs hfs;
+
+	/* Query for HSIO version, overloads H_GS and HFS */
+	pci_write_config32(PCH_DEV_ME, PCI_ME_H_GS,
+			   ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER);
+
+	/* Must wait for ME acknowledgement */
+	for (count = ME_RETRY; count > 0; --count) {
+		me_read_dword_ptr(&hfs, PCI_ME_HFS);
+		if (hfs.bios_msg_ack)
+			break;
+		udelay(ME_DELAY);
+	}
+	if (!count) {
+		printk(BIOS_ERR, "ERROR: ME failed to respond\n");
+		return;
+	}
+
+	/* HSIO version should be in HFS_5 */
+	hsiover = pci_read_config32(PCH_DEV_ME, PCI_ME_HFS5);
+	*version = hsiover >> 16;
+	*checksum = hsiover & 0xffff;
+
+	printk(BIOS_DEBUG, "ME: HSIO Version            : %d (CRC 0x%04x)\n",
+	       *version, *checksum);
+
+	/* Reset registers to normal behavior */
+	pci_write_config32(PCH_DEV_ME, PCI_ME_H_GS,
+			   ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER);
+}

src/soc/intel/broadwell/romstage/romstage.c

@@ -106,6 +106,10 @@ void romstage_common(struct romstage_params *params)
 	/* Print ME state before MRC */
 	intel_me_status();
 
+	/* Save ME HSIO version */
+	intel_me_hsio_version(&params->power_state->hsio_version,
+			      &params->power_state->hsio_checksum);
+
 	/* Initialize RAM */
 	raminit(params->pei_data);