CBMEM: Add config CBMEM_TOP_BACKUP

AGESA and binaryPI boards have no easy way to determine correct
cbmem_top() location early enough when GFXUMA is enabled, so they
will use these functions with EARLY_CBMEM_INIT as well.

At the end of AmdInitPost() the decisions of UMA base and size
have not been written to hardware yet. The decisions are stored
inside AGESA heap object we cannot locate from coreboot proper
until after AmdInitEnv().

Modify code such that weak backup functions are only defined
for LATE_CBMEM_INIT; they are somewhat troublesome to handle.

Change-Id: Ifef4f75b36bc6dee6cd56d1d9164281d9b2a4f2a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19306
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/arch/x86/Kconfig

@@ -111,8 +111,15 @@ config ROMCC
 	bool
 	default n
 
+config CBMEM_TOP_BACKUP
+	def_bool n
+	help
+	  Platform implements non-volatile storage to cache cbmem_top()
+	  over stage transitions and optionally also over S3 suspend.
+
 config LATE_CBMEM_INIT
 	def_bool n
+	select CBMEM_TOP_BACKUP
 	help
 	  Enable this in chipset's Kconfig if northbridge does not implement
 	  early get_top_of_ram() call for romstage. CBMEM tables will be

src/arch/x86/cbmem.c

@@ -18,49 +18,47 @@
 
 #if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
 
-#if !defined(__PRE_RAM__)
 void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop)
 {
 	/* Do nothing. Chipset may have implementation to save ramtop in NVRAM.
 	 */
 }
 
-static void *ramtop_pointer;
-
-void set_top_of_ram(uint64_t ramtop)
-{
-	backup_top_of_ram(ramtop);
-	ramtop_pointer = (void *)(uintptr_t)ramtop;
-}
-
-static inline void *saved_ramtop(void)
-{
-	return ramtop_pointer;
-}
-#else
-static inline void *saved_ramtop(void)
-{
-	return NULL;
-}
-#endif /* !__PRE_RAM__ */
-
 unsigned long __attribute__((weak)) get_top_of_ram(void)
 {
 	return 0;
 }
 
+#endif /* LATE_CBMEM_INIT */
+
+#if IS_ENABLED(CONFIG_CBMEM_TOP_BACKUP)
+
+static void *ramtop_pointer;
+
+void set_top_of_ram(uint64_t ramtop)
+{
+	backup_top_of_ram(ramtop);
+	if (ENV_RAMSTAGE)
+		ramtop_pointer = (void *)(uintptr_t)ramtop;
+}
+
 void *cbmem_top(void)
 {
 	/* Top of cbmem is at lowest usable DRAM address below 4GiB. */
-	void *ptr = saved_ramtop();
+	uintptr_t ramtop;
 
-	if (ptr != NULL)
-		return ptr;
+	if (ENV_RAMSTAGE && ramtop_pointer != NULL)
+		return ramtop_pointer;
 
-	return (void *)get_top_of_ram();
+	ramtop = get_top_of_ram();
+
+	if (ENV_RAMSTAGE)
+		ramtop_pointer = (void *)ramtop;
+
+	return (void *)ramtop;
 }
 
-#endif /* LATE_CBMEM_INIT */
+#endif /* CBMEM_TOP_BACKUP */
 
 /* Something went wrong, our high memory area got wiped */
 void cbmem_fail_resume(void)

src/include/cbmem.h

@@ -145,11 +145,12 @@ void cbmem_add_records_to_cbtable(struct lb_header *header);
 #endif /* ENV_RAMSTAGE */
 
 
-/* These are for compatibility with old boards only. Any new chipset and board
- * must implement cbmem_top() for both romstage and ramstage to support
- * early features like COLLECT_TIMESTAMPS and CBMEM_CONSOLE.
+/* Any new chipset and board must implement cbmem_top() for both
+ * romstage and ramstage to support early features like COLLECT_TIMESTAMPS
+ * and CBMEM_CONSOLE. Sometimes it is necessary to have cbmem_top()
+ * value stored in nvram to enable early recovery on S3 path.
  */
-#if IS_ENABLED(CONFIG_ARCH_X86) && IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
+#if IS_ENABLED(CONFIG_ARCH_X86)
 /* Note that many of the current providers of get_top_of_ram() conditionally
  * return 0 when the sleep type is non S3. i.e. cold and warm boots would
  * return 0 from get_top_of_ram(). */