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mb/google/brya/var/*: Add disable_gpio_export_in_crs to all devicetrees 

None of the touchscreens used in the brya program (any brya board)
should require exporting of GPIOs in the ACPI _CRS method for any i2c
device. This can cause i2c devices to malfunction or cause timing
sequence violations if:

1) ACPI exports a PowerResource for the device that uses GPIOs that are
   also exported in _CRS
2) The kernel driver for the device uses the GPIOs exported in _CRS for
   its own purposes. This means the state of the pin is out of sync
   between platform firmware and the kernel. The Linux ELAN I2C
   touchcsreen driver (https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/upstream/drivers/input/touchscreen/elants_i2c.c;l=1429)
   is one example of this.

Therefore, add disable_gpio_export_in_crs to all brya variants that use
the drivers/i2c/generic or drivers/i2c/hid chip drivers.

Change-Id: Ib4475bd0dc885e230911de6298fd95baa868ef29
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Tim Wawrzynczak 2021-12-16 11:17:07 -07:00 committed by Felix Held
parent 8140691742
commit a7e85d43c8
13 changed files with 20 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/brya/variants/anahera/overridetree.cb
View File

@ -215,6 +215,7 @@ chip soc/intel/alderlake
register "stop_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
register "has_power_resource" = "1"
register "disable_gpio_export_in_crs" = "1"
device i2c 10 on end
end
chip drivers/i2c/hid
@ -229,6 +230,7 @@ chip soc/intel/alderlake
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
register "generic.enable_delay_ms" = "1"
register "generic.has_power_resource" = "1"
register "generic.disable_gpio_export_in_crs" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 40 on end
end

2
src/mainboard/google/brya/variants/anahera4es/overridetree.cb
View File

@ -215,6 +215,7 @@ chip soc/intel/alderlake
register "stop_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
register "has_power_resource" = "1"
register "disable_gpio_export_in_crs" = "1"
device i2c 10 on end
end
chip drivers/i2c/hid
@ -229,6 +230,7 @@ chip soc/intel/alderlake
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
register "generic.enable_delay_ms" = "1"
register "generic.has_power_resource" = "1"
register "generic.disable_gpio_export_in_crs" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 40 on end
end

1
src/mainboard/google/brya/variants/felwinter/overridetree.cb
View File

@ -260,6 +260,7 @@ chip soc/intel/alderlake
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
register "generic.stop_off_delay_ms" = "1"
register "generic.has_power_resource" = "1"
register "generic.disable_gpio_export_in_crs" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 10 on end
end

1
src/mainboard/google/brya/variants/gimble/overridetree.cb
View File

@ -217,6 +217,7 @@ chip soc/intel/alderlake
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
register "generic.stop_off_delay_ms" = "1"
register "generic.has_power_resource" = "1"
register "generic.disable_gpio_export_in_crs" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 0x15 on end
end

1
src/mainboard/google/brya/variants/gimble4es/overridetree.cb
View File

@ -173,6 +173,7 @@ chip soc/intel/alderlake
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
register "generic.stop_off_delay_ms" = "1"
register "generic.has_power_resource" = "1"
register "generic.disable_gpio_export_in_crs" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 0x15 on end
end

1
src/mainboard/google/brya/variants/kano/overridetree.cb
View File

@ -425,6 +425,7 @@ chip soc/intel/alderlake
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
register "generic.stop_off_delay_ms" = "1"
register "generic.has_power_resource" = "1"
register "generic.disable_gpio_export_in_crs" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 0x10 on end
end

2
src/mainboard/google/brya/variants/primus/overridetree.cb
View File

@ -236,6 +236,7 @@ chip soc/intel/alderlake
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
register "generic.stop_off_delay_ms" = "1"
register "generic.has_power_resource" = "1"
register "generic.disable_gpio_export_in_crs" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 0x10 on end
end
@ -251,6 +252,7 @@ chip soc/intel/alderlake
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
register "generic.enable_delay_ms" = "1"
register "generic.has_power_resource" = "1"
register "generic.disable_gpio_export_in_crs" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 0x40 on end
end

2
src/mainboard/google/brya/variants/primus4es/overridetree.cb
View File

@ -223,6 +223,7 @@ chip soc/intel/alderlake
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
register "generic.stop_off_delay_ms" = "1"
register "generic.has_power_resource" = "1"
register "generic.disable_gpio_export_in_crs" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 0x10 on end
end
@ -238,6 +239,7 @@ chip soc/intel/alderlake
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
register "generic.enable_delay_ms" = "1"
register "generic.has_power_resource" = "1"
register "generic.disable_gpio_export_in_crs" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 0x40 on end
end

1
src/mainboard/google/brya/variants/redrix/overridetree.cb
View File

@ -386,6 +386,7 @@ chip soc/intel/alderlake
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
register "generic.stop_off_delay_ms" = "1"
register "generic.has_power_resource" = "1"
register "generic.disable_gpio_export_in_crs" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 0x15 on end
end

1
src/mainboard/google/brya/variants/redrix4es/overridetree.cb
View File

@ -270,6 +270,7 @@ chip soc/intel/alderlake
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
register "generic.stop_off_delay_ms" = "1"
register "generic.has_power_resource" = "1"
register "generic.disable_gpio_export_in_crs" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 0x15 on end
end

2
src/mainboard/google/brya/variants/taeko/overridetree.cb
View File

@ -292,6 +292,7 @@ chip soc/intel/alderlake
# Parameter T4 >= 1ms
register "generic.stop_off_delay_ms" = "1"
register "generic.has_power_resource" = "1"
register "generic.disable_gpio_export_in_crs" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 5d on end
end
@ -307,6 +308,7 @@ chip soc/intel/alderlake
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
register "enable_delay_ms" = "1"
register "has_power_resource" = "1"
register "disable_gpio_export_in_crs" = "1"
device i2c 10 on end
end
end

2
src/mainboard/google/brya/variants/taeko4es/overridetree.cb
View File

@ -292,6 +292,7 @@ chip soc/intel/alderlake
# Parameter T4 >= 1ms
register "generic.stop_off_delay_ms" = "1"
register "generic.has_power_resource" = "1"
register "generic.disable_gpio_export_in_crs" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 5d on end
end
@ -307,6 +308,7 @@ chip soc/intel/alderlake
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
register "enable_delay_ms" = "1"
register "has_power_resource" = "1"
register "disable_gpio_export_in_crs" = "1"
device i2c 10 on end
end
end

2
src/mainboard/google/brya/variants/vell/overridetree.cb
View File

@ -191,6 +191,7 @@ chip soc/intel/alderlake
register "stop_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
register "has_power_resource" = "1"
register "disable_gpio_export_in_crs" = "1"
device i2c 10 on end
end
chip drivers/i2c/hid
@ -205,6 +206,7 @@ chip soc/intel/alderlake
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
register "generic.enable_delay_ms" = "1"
register "generic.has_power_resource" = "1"
register "generic.disable_gpio_export_in_crs" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 40 on end
end