From a7ec42619c310a5e72256821d17f62e7e64bce45 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 11 Mar 2020 16:31:59 +0100 Subject: [PATCH] soc/intel/*/smihandler: Only compile in TCO SMI handler if needed MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 7f9ceef disables TCO SMIs unless specifically enabled, so help the linker throw out the function that handles them in that case. Change-Id: Ia3c93b46e979fb8b99282875b188415f249d38dd Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/39452 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Michael Niewöhner --- src/soc/intel/apollolake/smihandler.c | 2 ++ src/soc/intel/cannonlake/smihandler.c | 2 ++ src/soc/intel/icelake/smihandler.c | 2 ++ src/soc/intel/skylake/smihandler.c | 2 ++ src/soc/intel/tigerlake/smihandler.c | 2 ++ 5 files changed, 10 insertions(+) diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c index e37de92d2a..073d66590d 100644 --- a/src/soc/intel/apollolake/smihandler.c +++ b/src/soc/intel/apollolake/smihandler.c @@ -39,7 +39,9 @@ const smi_handler_t southbridge_smi[32] = { [APM_STS_BIT] = smihandler_southbridge_apmc, [PM1_STS_BIT] = smihandler_southbridge_pm1, [GPIO_STS_BIT] = smihandler_southbridge_gpi, +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) [TCO_STS_BIT] = smihandler_southbridge_tco, +#endif [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, #if CONFIG(SOC_ESPI) [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index 4be7897f78..f68f4c29bf 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -48,7 +48,9 @@ const smi_handler_t southbridge_smi[SMI_STS_BITS] = { [GPIO_STS_BIT] = smihandler_southbridge_gpi, [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, [MCSMI_STS_BIT] = smihandler_southbridge_mc, +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) [TCO_STS_BIT] = smihandler_southbridge_tco, +#endif [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, [MONITOR_STS_BIT] = smihandler_southbridge_monitor, }; diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index 6be7b70338..ec9deb2858 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -46,7 +46,9 @@ const smi_handler_t southbridge_smi[SMI_STS_BITS] = { [GPIO_STS_BIT] = smihandler_southbridge_gpi, [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, [MCSMI_STS_BIT] = smihandler_southbridge_mc, +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) [TCO_STS_BIT] = smihandler_southbridge_tco, +#endif [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, [MONITOR_STS_BIT] = smihandler_southbridge_monitor, }; diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index 4818c0202e..213de0ac00 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -26,7 +26,9 @@ const smi_handler_t southbridge_smi[SMI_STS_BITS] = { [GPIO_STS_BIT] = smihandler_southbridge_gpi, [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, [MCSMI_STS_BIT] = smihandler_southbridge_mc, +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) [TCO_STS_BIT] = smihandler_southbridge_tco, +#endif [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, [MONITOR_STS_BIT] = smihandler_southbridge_monitor, }; diff --git a/src/soc/intel/tigerlake/smihandler.c b/src/soc/intel/tigerlake/smihandler.c index 0e8d345bac..1eb56aac8d 100644 --- a/src/soc/intel/tigerlake/smihandler.c +++ b/src/soc/intel/tigerlake/smihandler.c @@ -46,7 +46,9 @@ const smi_handler_t southbridge_smi[SMI_STS_BITS] = { [GPIO_STS_BIT] = smihandler_southbridge_gpi, [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, [MCSMI_STS_BIT] = smihandler_southbridge_mc, +#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) [TCO_STS_BIT] = smihandler_southbridge_tco, +#endif [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, [MONITOR_STS_BIT] = smihandler_southbridge_monitor, };