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arch/x86: Correctly determine number of enabled cores 

Instead of using MAX of (cores_enabled, MAX_CPUS), use MIN
which is correct.

TEST=tested with dmidecode

Change-Id: Id0935f48e73c037bb7c0e1cf36f94d98a40a499c
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Andrey Petrov 2019-11-07 09:48:41 -08:00
parent a2d123ea98
commit a7fb23081c
1 changed files with 1 additions and 1 deletions
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2
src/arch/x86/smbios.c
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@ -659,7 +659,7 @@ static int smbios_write_type4(unsigned long *current, int handle)
t->processor_type = 3; /* System Processor */ t->processor_type = 3; /* System Processor */
t->core_count = (res.ebx >> 16) & 0xff; t->core_count = (res.ebx >> 16) & 0xff;
/* Assume we enable all the cores always, capped only by MAX_CPUS */ /* Assume we enable all the cores always, capped only by MAX_CPUS */
t->core_enabled = MAX(t->core_count, CONFIG_MAX_CPUS); t->core_enabled = MIN(t->core_count, CONFIG_MAX_CPUS);
t->l1_cache_handle = 0xffff; t->l1_cache_handle = 0xffff;
t->l2_cache_handle = 0xffff; t->l2_cache_handle = 0xffff;
t->l3_cache_handle = 0xffff; t->l3_cache_handle = 0xffff;