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intel/skylake: Remove unused devicetree configuration variables 

The GPU panel configuration variables are unused on skylake
and are no longer needed in chip.h.

BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-chell coreboot

Change-Id: Ie6bfb676b5a32b4d4d39dda91b90fc7e973d38e0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f261d7ca9ec93aae1362975efde11ac9657b7ca6
Original-Change-Id: If64594455754e4dea1f53511861b74ddd880c5b5
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/318923
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12986
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Duncan Laurie 2015-12-16 16:34:19 -08:00 committed by Patrick Georgi
parent 758c171539
commit a7feb9fa2d
1 changed files with 0 additions and 23 deletions
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23
src/soc/intel/skylake/chip.h
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@ -58,29 +58,6 @@ struct soc_intel_skylake_config {
uint32_t gen3_dec;
uint32_t gen4_dec;
/*
* Digital Port Hotplug Enable:
* 0x04 = Enabled, 2ms short pulse
* 0x05 = Enabled, 4.5ms short pulse
* 0x06 = Enabled, 6ms short pulse
* 0x07 = Enabled, 100ms short pulse
*/
u8 gpu_dp_b_hotplug;
u8 gpu_dp_c_hotplug;
u8 gpu_dp_d_hotplug;
/* Panel power sequence timings */
u8 gpu_panel_port_select;
u8 gpu_panel_power_cycle_delay;
u16 gpu_panel_power_up_delay;
u16 gpu_panel_power_down_delay;
u16 gpu_panel_power_backlight_on_delay;
u16 gpu_panel_power_backlight_off_delay;
/* Panel backlight settings */
u32 gpu_cpu_backlight;
u32 gpu_pch_backlight;
/* Enable S0iX support */
int s0ix_enable;