mb/google/hades: Change memory to SODIMM

Add SODIMM support, drop the solderdown based on schematics.

BUG=b:271199379
TEST=abuild -a -x -c max -p none -t google/brya -b hades

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I85ec79c3d8f1147a875c4d04017bb50347121ebb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>

src/mainboard/google/brya/Kconfig

@@ -67,7 +67,7 @@ config BOARD_GOOGLE_BASEBOARD_HADES
 	select BOARD_GOOGLE_BRYA_COMMON
 	select BOARD_ROMSIZE_KB_32768
 	select HAVE_SLP_S0_GATE
-	select MEMORY_SOLDERDOWN
+	select MEMORY_SODIMM
 	select SOC_INTEL_ALDERLAKE_PCH_P
 	select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY
 	select SOC_INTEL_RAPTORLAKE

src/mainboard/google/brya/variants/baseboard/hades/memory.c

@@ -3,102 +3,41 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <gpio.h>
+#include <soc/romstage.h>
 
-/* TODO: Set the correct values */
+static const struct mb_cfg ddr5_mem_config = {
-static const struct mb_cfg baseboard_memcfg = {
+	.type = MEM_TYPE_DDR5,
-	.type = MEM_TYPE_LP4X,
 
 	.rcomp = {
 		/* Baseboard uses only 100ohm Rcomp resistors */
 		.resistor = 100,
 
 		/* Baseboard Rcomp target values */
-		.targets = {40, 30, 30, 30, 30},
+		.targets = {50, 20, 25, 25, 25},
 	},
 
-	/* DQ byte map */
+	.ect = 1, /* Early Command Training */
-	.lpx_dq_map = {
-		.ddr0 = {
-			.dq0 = {  9, 11,  8, 10, 12, 14, 13, 15, },
-			.dq1 = {  4,  7,  6,  5,  2,  3,  0,  1, },
-		},
-		.ddr1 = {
-			.dq0 = { 15, 12, 14, 13,  9, 10, 11,  8, },
-			.dq1 = {  0,  1,  3,  2,  7,  5,  4,  6, },
-		},
-		.ddr2 = {
-			.dq0 = {  2,  3,  1,  0,  6,  7,  5,  4, },
-			.dq1 = { 15,  9, 14,  8, 11, 10, 13, 12, },
-		},
-		.ddr3 = {
-			.dq0 = {  3,  1,  2,  0,  4,  6,  7,  5, },
-			.dq1 = { 13, 15, 14, 12, 11,  9,  8, 10, },
-		},
-		.ddr4 = {
-			.dq0 = { 13, 12, 14, 15,  9,  8, 10, 11, },
-			.dq1 = {  4,  7,  5,  6,  1,  2,  0,  3, },
-		},
-		.ddr5 = {
-			.dq0 = {  5,  0,  6,  4,  3,  1,  7,  2, },
-			.dq1 = { 11,  9, 10,  8, 15, 12, 14, 13, },
-		},
-		.ddr6 = {
-			.dq0 = { 15, 12, 14, 13, 10,  9, 11,  8, },
-			.dq1 = {  0,  1,  2,  3,  5,  6,  4,  7, },
-		},
-		.ddr7 = {
-			.dq0 = {  0,  3,  1,  2,  4,  5,  6,  7, },
-			.dq1 = { 11,  8, 13, 14,  9, 12, 15, 10, },
-		},
-	},
 
-	/* DQS CPU<>DRAM map */
+	.UserBd = BOARD_TYPE_MOBILE,
-	.lpx_dqs_map = {
-		.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
-		.ddr1 = { .dqs0 = 1, .dqs1 = 0 },
-		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
-		.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
-		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
-		.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
-	},
 
-	.ect = 1, /* Enable Early Command Training */
+	.ddr_config = {
+		.dq_pins_interleaved = false,
+	},
 };
 
 const struct mb_cfg *__weak variant_memory_params(void)
 {
-	return &baseboard_memcfg;
+	return &ddr5_mem_config;
-}
-
-int __weak variant_memory_sku(void)
-{
-	/*
-	 * Memory configuration board straps
-	 * GPIO_MEM_CONFIG_0	GPP_E11
-	 * GPIO_MEM_CONFIG_1	GPP_E2
-	 * GPIO_MEM_CONFIG_2	GPP_E1
-	 * GPIO_MEM_CONFIG_3	GPP_E12
-	 */
-	gpio_t spd_gpios[] = {
-		GPP_E11,
-		GPP_E2,
-		GPP_E1,
-		GPP_E12,
-	};
-
-	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
 }
 
 bool __weak variant_is_half_populated(void)
 {
-	/* GPIO_MEM_CH_SEL GPP_E13 */
+	return false;
-	return gpio_get(GPP_E13);
 }
 
 void __weak variant_get_spd_info(struct mem_spd *spd_info)
 {
-	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+	spd_info->topo = MEM_TOPO_DIMM_MODULE;
-	spd_info->cbfs_index = variant_memory_sku();
+	spd_info->smbus[0].addr_dimm[0] = 0x50;
+	spd_info->smbus[1].addr_dimm[0] = 0x52;
 }

src/mainboard/google/brya/variants/hades/memory/Makefile.inc

@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-or-later
-
-SPD_SOURCES =
-SPD_SOURCES += spd/lp4x/set-0/spd-empty.hex      # dummy SPD