diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c
index fbf74468b0..8668110713 100644
--- a/src/superio/ite/common/env_ctrl.c
+++ b/src/superio/ite/common/env_ctrl.c
@@ -264,6 +264,13 @@ void ite_ec_init(const u16 base, const struct ite_ec_config *const conf)
 				ITE_EC_INTERFACE_SMB_ENABLE);
 	}
 
+	/* Set SST/PECI Host Controller Clock to either 24 MHz or internal 32 MHz */
+	if (conf->smbus_24mhz) {
+		pnp_write_hwm5_index(base, ITE_EC_INTERFACE_SELECT,
+			pnp_read_hwm5_index(base, ITE_EC_INTERFACE_SELECT) |
+				ITE_EC_INTERFACE_CLOCK_24MHZ);
+	}
+
 	/* Enable reading of voltage pins */
 	pnp_write_hwm5_index(base, ITE_EC_ADC_VOLTAGE_CHANNEL_ENABLE, conf->vin_mask);
 
diff --git a/src/superio/ite/common/env_ctrl_chip.h b/src/superio/ite/common/env_ctrl_chip.h
index 09577a4d84..fa896e4074 100644
--- a/src/superio/ite/common/env_ctrl_chip.h
+++ b/src/superio/ite/common/env_ctrl_chip.h
@@ -91,6 +91,11 @@ struct ite_ec_config {
 	 * Enable SMBus for external thermal sensor.
 	 */
 	bool smbus_en;
+	/*
+	 * Select 24 MHz clock for external host instead of an
+	 * internally generated 32 MHz clock.
+	 */
+	bool smbus_24mhz;
 };
 
 /* Some shorthands for device trees */