mb/google/hatch: Add Noibat variant
A verbatim copy of variants/puff. BUG=b:156429564 BRANCH=none TEST=none Change-Id: I8c76d468177e1f3fcab53e0790599041b1a944d8 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41851 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Edward O'Callaghan
Edward O'Callaghan
parent
fc3eb1ca1d
commit
a81be27dc5
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@ -124,6 +124,7 @@ config MAINBOARD_PART_NUMBER
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default "Kindred" if BOARD_GOOGLE_KINDRED
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default "Kohaku" if BOARD_GOOGLE_KOHAKU
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default "Mushu" if BOARD_GOOGLE_MUSHU
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default "Noibat" if BOARD_GOOGLE_NOIBAT
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default "Palkia" if BOARD_GOOGLE_PALKIA
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default "Nightfury" if BOARD_GOOGLE_NIGHTFURY
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default "Puff" if BOARD_GOOGLE_PUFF
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@ -154,6 +155,7 @@ config VARIANT_DIR
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default "kindred" if BOARD_GOOGLE_KINDRED
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default "kohaku" if BOARD_GOOGLE_KOHAKU
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default "mushu" if BOARD_GOOGLE_MUSHU
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default "noibat" if BOARD_GOOGLE_NOIBAT
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default "palkia" if BOARD_GOOGLE_PALKIA
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default "nightfury" if BOARD_GOOGLE_NIGHTFURY
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default "puff" if BOARD_GOOGLE_PUFF
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@ -67,6 +67,10 @@ config BOARD_GOOGLE_NIGHTFURY
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select CHROMEOS_DSM_CALIB
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select DRIVERS_I2C_MAX98390
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config BOARD_GOOGLE_NOIBAT
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bool "-> Noibat"
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select BOARD_GOOGLE_BASEBOARD_PUFF
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config BOARD_GOOGLE_PUFF
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bool "-> Puff"
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select BOARD_GOOGLE_BASEBOARD_PUFF
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@ -0,0 +1,5 @@
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## SPDX-License-Identifier: GPL-2.0-only
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ramstage-y += gpio.c
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ramstage-y += mainboard.c
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bootblock-y += gpio.c
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@ -0,0 +1,115 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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static const struct pad_config gpio_table[] = {
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/* A16 : SD_OC_ODL */
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PAD_CFG_GPI(GPP_A16, NONE, DEEP),
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/* A18 : LAN_PE_ISOLATE_ODL */
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PAD_CFG_GPO(GPP_A18, 1, DEEP),
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/* A23 : M2_WLAN_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT),
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/* B5 : LAN_CLKREQ_ODL */
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PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
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/* C0 : SMBCLK */
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PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
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/* C1 : SMBDATA */
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PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
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/* C6: M2_WLAN_WAKE_ODL */
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PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE),
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/* C7 : LAN_WAKE_ODL */
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PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE),
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/* C10 : PCH_PCON_RST_ODL */
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PAD_CFG_GPO(GPP_C10, 1, DEEP),
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/* C11 : PCH_PCON_PDB_ODL */
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PAD_CFG_GPO(GPP_C11, 1, DEEP),
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/* C15 : WLAN_OFF_L */
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PAD_CFG_GPO(GPP_C15, 1, DEEP),
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/* E2 : EN_PP_MST_OD */
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PAD_CFG_GPO(GPP_E2, 1, DEEP),
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/* E9 : USB_A0_OC_ODL */
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PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
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/* E10 : USB_A1_OC_ODL */
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PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
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/* F11 : EMMC_CMD */
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PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
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/* F12 : EMMC_DATA0 */
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PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
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/* F13 : EMMC_DATA1 */
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PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
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/* F14 : EMMC_DATA2 */
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PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
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/* F15 : EMMC_DATA3 */
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PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
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/* F16 : EMMC_DATA4 */
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PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
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/* F17 : EMMC_DATA5 */
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PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
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/* F18 : EMMC_DATA6 */
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PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
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/* F19 : EMMC_DATA7 */
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PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
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/* F20 : EMMC_RCLK */
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PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
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/* F21 : EMMC_CLK */
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PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
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/* F22 : EMMC_RST_L */
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PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
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/* H4: PCH_I2C_PCON_SDA */
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PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
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/* H5: PCH_I2C_PCON_SCL */
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PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
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/* H22 : PWM_PP3300_BIOZZER */
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PAD_CFG_GPO(GPP_H22, 0, DEEP),
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};
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const struct pad_config *override_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(gpio_table);
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return gpio_table;
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}
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* B14 : GPP_B14_STRAP */
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PAD_NC(GPP_B14, NONE),
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/* B22 : GPP_B22_STRAP */
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PAD_NC(GPP_B22, NONE),
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/* E19 : GPP_E19_STRAP */
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PAD_NC(GPP_E19, NONE),
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/* E21 : GPP_E21_STRAP */
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PAD_NC(GPP_E21, NONE),
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/* B15 : H1_SLAVE_SPI_CS_L */
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PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
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/* B16 : H1_SLAVE_SPI_CLK */
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PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
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/* B17 : H1_SLAVE_SPI_MISO_R */
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* B18 : H1_SLAVE_SPI_MOSI_R */
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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/* C14 : BT_DISABLE_L */
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PAD_CFG_GPO(GPP_C14, 0, DEEP),
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/* PCH_WP_OD */
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PAD_CFG_GPI(GPP_C20, NONE, DEEP),
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/* C21 : H1_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
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/* C23 : WLAN_PE_RST# */
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PAD_CFG_GPO(GPP_C23, 1, DEEP),
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/* E1 : M2_SSD_PEDET */
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PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
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/* E5 : SATA_DEVSLP1 */
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PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
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};
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const struct pad_config *variant_early_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(early_gpio_table);
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return early_gpio_table;
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}
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@ -0,0 +1,114 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#define DPTF_CPU_PASSIVE 93
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#define DPTF_CPU_CRITICAL 100
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#define DPTF_CPU_ACTIVE_AC0 90
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#define DPTF_CPU_ACTIVE_AC1 85
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#define DPTF_CPU_ACTIVE_AC2 80
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#define DPTF_CPU_ACTIVE_AC3 75
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#define DPTF_CPU_ACTIVE_AC4 70
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#define DPTF_CPU_ACTIVE_AC5 65
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#define DPTF_TSR0_SENSOR_ID 0
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#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1"
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#define DPTF_TSR0_PASSIVE 65
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#define DPTF_TSR0_CRITICAL 75
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#define DPTF_TSR0_ACTIVE_AC0 50
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#define DPTF_TSR0_ACTIVE_AC1 47
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#define DPTF_TSR0_ACTIVE_AC2 45
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#define DPTF_TSR0_ACTIVE_AC3 42
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#define DPTF_TSR0_ACTIVE_AC4 39
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#define DPTF_TSR1_SENSOR_ID 1
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#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2"
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#define DPTF_TSR1_PASSIVE 65
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#define DPTF_TSR1_CRITICAL 75
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#define DPTF_TSR1_ACTIVE_AC0 50
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#define DPTF_TSR1_ACTIVE_AC1 47
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#define DPTF_TSR1_ACTIVE_AC2 45
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#define DPTF_TSR1_ACTIVE_AC3 42
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#define DPTF_TSR1_ACTIVE_AC4 39
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#define DPTF_ENABLE_CHARGER
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#define DPTF_ENABLE_FAN_CONTROL
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/* Charger performance states, board-specific values from charger and EC */
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Name (CHPS, Package () {
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Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */
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Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
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Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
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Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
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})
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/* DFPS: Fan Performance States */
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Name (DFPS, Package () {
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0, // Revision
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/*
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* TODO : Need to update this Table after characterization.
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* These are initial reference values.
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*/
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/* Control, Trip Point, Speed, NoiseLevel, Power */
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Package () {90, 0xFFFFFFFF, 6700, 220, 2200},
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Package () {80, 0xFFFFFFFF, 5800, 180, 1800},
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Package () {70, 0xFFFFFFFF, 5000, 145, 1450},
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Package () {60, 0xFFFFFFFF, 4900, 115, 1150},
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Package () {50, 0xFFFFFFFF, 3838, 90, 900},
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Package () {40, 0xFFFFFFFF, 2904, 55, 550},
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Package () {30, 0xFFFFFFFF, 2337, 30, 300},
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Package () {20, 0xFFFFFFFF, 1608, 15, 150},
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Package () {10, 0xFFFFFFFF, 800, 10, 100},
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Package () {0, 0xFFFFFFFF, 0, 0, 50}
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})
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Name (DART, Package () {
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/* Fan effect on CPU */
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0, // Revision
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Package () {
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/*
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* Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6,
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* AC7, AC8, AC9
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*/
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\_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 95, 85, 75, 65, 55, 45, 0, 0,
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0, 0, 0
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},
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Package () {
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 95, 85, 75, 65, 55, 45, 0, 0,
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0, 0, 0
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},
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Package () {
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 95, 85, 75, 65, 55, 45, 0, 0,
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0, 0, 0
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}
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})
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Name (DTRT, Package () {
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/* CPU Throttle Effect on CPU */
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Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },
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/* CPU Throttle Effect on Ambient (TSR0) */
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Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 },
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/* Charger Throttle Effect on Charger (TSR1) */
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Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 },
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})
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Name (MPPC, Package ()
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{
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0x2, /* Revision */
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Package () { /* Power Limit 1 */
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0, /* PowerLimitIndex, 0 for Power Limit 1 */
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15000, /* PowerLimitMinimum */
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15000, /* PowerLimitMaximum */
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28000, /* TimeWindowMinimum */
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32000, /* TimeWindowMaximum */
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200 /* StepSize */
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},
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Package () { /* Power Limit 2 */
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1, /* PowerLimitIndex, 1 for Power Limit 2 */
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25000, /* PowerLimitMinimum */
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64000, /* PowerLimitMaximum */
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28000, /* TimeWindowMinimum */
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32000, /* TimeWindowMaximum */
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1000 /* StepSize */
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}
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})
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@ -0,0 +1,59 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef VARIANT_EC_H
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#define VARIANT_EC_H
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#include <ec/google/chromeec/ec_commands.h>
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#include <variant/gpio.h>
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#define MAINBOARD_EC_SCI_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
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#define MAINBOARD_EC_SMI_EVENTS 0
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/* EC can wake from S5 with power button */
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#define MAINBOARD_EC_S5_WAKE_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
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/* EC can wake from S3 with power button */
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#define MAINBOARD_EC_S3_WAKE_EVENTS (MAINBOARD_EC_S5_WAKE_EVENTS)
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#define MAINBOARD_EC_S0IX_WAKE_EVENTS \
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(MAINBOARD_EC_S3_WAKE_EVENTS | \
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT))
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/* Log EC wake events plus EC shutdown events */
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#define MAINBOARD_EC_LOG_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
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/*
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* ACPI related definitions for ASL code.
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*/
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/* Enable cros_ec_keyb device */
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#define EC_ENABLE_MKBP_DEVICE
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/* Enable EC backed PD MCU device in ACPI */
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#define EC_ENABLE_PD_MCU_DEVICE
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/*
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* Defines EC wake pin route.
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* Note that GPE_EC_WAKE is defined, confusingly, as GPE_LAN_WAK which is GPD2/LAN_WAKE#
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* on the PCH or as the line EC_PCH_WAKE_ODL on the schematic.
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*/
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#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
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#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
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#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
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/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */
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#define EC_ENABLE_SYNC_IRQ
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#endif /* VARIANT_EC_H */
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@ -0,0 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef VARIANT_GPIO_H
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#define VARIANT_GPIO_H
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#include <baseboard/gpio.h>
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#endif
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@ -0,0 +1,143 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <baseboard/variants.h>
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#include <chip.h>
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#include <delay.h>
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#include <device/device.h>
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#include <ec/google/chromeec/ec.h>
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#include <gpio.h>
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#include <intelblocks/power_limit.h>
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#include <timer.h>
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#define GPIO_HDMI_HPD GPP_E13
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#define GPIO_DP_HPD GPP_E14
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/* TODO: This can be moved to common directory */
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static void wait_for_hpd(gpio_t gpio, long timeout)
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{
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struct stopwatch sw;
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printk(BIOS_INFO, "Waiting for HPD\n");
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stopwatch_init_msecs_expire(&sw, timeout);
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while (!gpio_get(gpio)) {
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if (stopwatch_expired(&sw)) {
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printk(BIOS_WARNING,
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"HPD not ready after %ldms. Abort.\n", timeout);
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return;
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}
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mdelay(200);
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}
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printk(BIOS_INFO, "HPD ready after %lu ms\n",
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stopwatch_duration_msecs(&sw));
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}
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/*
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* For type-C chargers, set PL2 to 90% of max power to account for
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* cable loss and FET Rdson loss in the path from the source.
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*/
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#define SET_PSYSPL2(w) (9 * (w) / 10)
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#define PUFF_PL2 (35)
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#define PUFF_PSYSPL2 (58)
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#define PUFF_MAX_TIME_WINDOW 6
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#define PUFF_MIN_DUTYCYCLE 4
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/*
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* mainboard_set_power_limits
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*
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* Set Pl2 and SysPl2 values based on detected charger.
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* Values are defined below but we use U22 value for all SKUs for now.
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* definitions:
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* x = no value entered. Use default value in parenthesis.
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* will set 0 to anything that shouldn't be set.
|
||||
* n = max value of power adapter.
|
||||
* +-------------+-----+---------+-----------+-------+
|
||||
* | sku_id | PL2 | PsysPL2 | PsysPL3 | PL4 |
|
||||
* +-------------+-----+---------+-----------+-------+
|
||||
* | i7 U42 | 51 | 81 | x(.85PL4) | x(82) |
|
||||
* | celeron U22 | 35 | 58 | x(.85PL4) | x(51) |
|
||||
* +-------------+-----+---------+-----------+-------+
|
||||
* For USB C charger:
|
||||
* +-------------+-----+---------+---------+-------+
|
||||
* | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 |
|
||||
* +-------------+-----+---------+---------+-------+
|
||||
* | 60 (U42) | 44 | 54 | 54 | 54 |
|
||||
* | 60 (U22) | 29 | 54 | 54 | x(43) |
|
||||
* | n (U42) | 44 | .9n | .9n | .9n |
|
||||
* | n (U22) | 29 | .9n | .9n | x(43) |
|
||||
* +-------------+-----+---------+---------+-------+
|
||||
*/
|
||||
|
||||
/*
|
||||
* Psys_pmax considerations
|
||||
*
|
||||
* Given the hardware design in puff, the serial shunt resistor is 0.01ohm.
|
||||
* The full scale of hardware PSYS signal 0.8v maps to system current 9.6A
|
||||
* instead of real system power. The equation is shown below:
|
||||
* PSYS = 0.8v = (0.01ohm x Iinput) x 50 (INA213, gain 50V/V) x 15k/(15k + 75k)
|
||||
* Hence, Iinput (Amps) = 9.6A
|
||||
* Since there is no voltage information from PSYS, different voltage input
|
||||
* would map to different Psys_pmax settings:
|
||||
* For Type-C 15V, the Psys_pmax sholud be 15v x 9.6A = 144W
|
||||
* For Type-C 20V, the Psys_pmax should be 20v x 9.6A = 192W
|
||||
* For a barral jack, the Psys_pmax should be 19v x 9.6A = 182.4W
|
||||
*/
|
||||
#define PSYS_IMAX 9600
|
||||
#define BJ_VOLTS_MV 19000
|
||||
|
||||
static void mainboard_set_power_limits(struct soc_power_limits_config *conf)
|
||||
{
|
||||
enum usb_chg_type type;
|
||||
u32 watts;
|
||||
u16 volts_mv, current_ma;
|
||||
u32 psyspl2 = PUFF_PSYSPL2; // default barrel jack value for U22
|
||||
int rv = google_chromeec_get_usb_pd_power_info(&type, ¤t_ma, &volts_mv);
|
||||
|
||||
/* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/
|
||||
conf->tdp_psyspl3 = 0;
|
||||
conf->tdp_pl4 = 0;
|
||||
|
||||
if (rv == 0 && type == USB_CHG_TYPE_PD) {
|
||||
/* Detected USB-PD. Base on max value of adapter */
|
||||
watts = ((u32)current_ma * volts_mv) / 1000000;
|
||||
psyspl2 = watts;
|
||||
conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2);
|
||||
/* set max possible time window */
|
||||
conf->tdp_psyspl3_time = PUFF_MAX_TIME_WINDOW;
|
||||
/* set minimum duty cycle */
|
||||
conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE;
|
||||
conf->tdp_pl4 = SET_PSYSPL2(psyspl2);
|
||||
} else {
|
||||
/* Input type is barrel jack */
|
||||
volts_mv = BJ_VOLTS_MV;
|
||||
}
|
||||
/* voltage unit is milliVolts and current is in milliAmps */
|
||||
conf->psys_pmax = (u16)(((u32)PSYS_IMAX * volts_mv) / 1000000);
|
||||
|
||||
conf->tdp_pl2_override = PUFF_PL2;
|
||||
/* set psyspl2 to 90% of max adapter power */
|
||||
conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2);
|
||||
}
|
||||
|
||||
void variant_ramstage_init(void)
|
||||
{
|
||||
static const long display_timeout_ms = 3000;
|
||||
struct soc_power_limits_config *soc_config;
|
||||
config_t *conf = config_of_soc();
|
||||
|
||||
/* This is reconfigured back to whatever FSP-S expects by gpio_configure_pads. */
|
||||
gpio_input(GPIO_HDMI_HPD);
|
||||
gpio_input(GPIO_DP_HPD);
|
||||
if (display_init_required()
|
||||
&& !gpio_get(GPIO_HDMI_HPD)
|
||||
&& !gpio_get(GPIO_DP_HPD)) {
|
||||
/* This has to be done before FSP-S runs. */
|
||||
if (google_chromeec_wait_for_displayport(display_timeout_ms))
|
||||
wait_for_hpd(GPIO_DP_HPD, display_timeout_ms);
|
||||
}
|
||||
/* Psys_pmax needs to be setup before FSP-S */
|
||||
soc_config = &conf->power_limits_config;
|
||||
mainboard_set_power_limits(soc_config);
|
||||
}
|
||||
|
|
@ -0,0 +1,392 @@
|
|||
chip soc/intel/cannonlake
|
||||
# Enable heci communication
|
||||
register "HeciEnabled" = "1"
|
||||
|
||||
# Auto-switch between X4 NVMe and X2 NVMe.
|
||||
register "TetonGlacierMode" = "1"
|
||||
|
||||
register "SerialIoDevMode" = "{
|
||||
[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexI2C2] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C3] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C4] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C5] = PchSerialIoPci,
|
||||
[PchSerialIoIndexSPI0] = PchSerialIoPci,
|
||||
[PchSerialIoIndexSPI1] = PchSerialIoPci,
|
||||
[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
|
||||
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
|
||||
}"
|
||||
|
||||
# USB configuration
|
||||
# NOTE: This only applies to Puff,
|
||||
# usb2_ports[1] and usb2_ports[3] were swapped on
|
||||
# reference schematics after Puff has been built.
|
||||
register "usb2_ports[0]" = "{
|
||||
.enable = 1,
|
||||
.ocpin = OC2,
|
||||
.tx_bias = USB2_BIAS_0MV,
|
||||
.tx_emp_enable = USB2_PRE_EMP_ON,
|
||||
.pre_emp_bias = USB2_BIAS_11P25MV,
|
||||
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
|
||||
}" # Type-A Port 2
|
||||
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
|
||||
register "usb2_ports[2]" = "{
|
||||
.enable = 1,
|
||||
.ocpin = OC3,
|
||||
.tx_bias = USB2_BIAS_0MV,
|
||||
.tx_emp_enable = USB2_PRE_EMP_ON,
|
||||
.pre_emp_bias = USB2_BIAS_28P15MV,
|
||||
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
|
||||
}" # Type-A Port 3
|
||||
register "usb2_ports[3]" = "{
|
||||
.enable = 1,
|
||||
.ocpin = OC1,
|
||||
.tx_bias = USB2_BIAS_0MV,
|
||||
.tx_emp_enable = USB2_PRE_EMP_ON,
|
||||
.pre_emp_bias = USB2_BIAS_28P15MV,
|
||||
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
|
||||
}" # Type-A Port 1
|
||||
register "usb2_ports[4]" = "{
|
||||
.enable = 1,
|
||||
.ocpin = OC_SKIP,
|
||||
.tx_bias = USB2_BIAS_0MV,
|
||||
.tx_emp_enable = USB2_PRE_EMP_ON,
|
||||
.pre_emp_bias = USB2_BIAS_28P15MV,
|
||||
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
|
||||
}" # Type-A Port 4
|
||||
register "usb2_ports[5]" = "{
|
||||
.enable = 1,
|
||||
.ocpin = OC0,
|
||||
.tx_bias = USB2_BIAS_0MV,
|
||||
.tx_emp_enable = USB2_PRE_EMP_ON,
|
||||
.pre_emp_bias = USB2_BIAS_28P15MV,
|
||||
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
|
||||
}" # Type-A port 0
|
||||
register "usb2_ports[6]" = "USB2_PORT_EMPTY"
|
||||
register "usb2_ports[7]" = "USB2_PORT_EMPTY"
|
||||
register "usb2_ports[8]" = "USB2_PORT_EMPTY"
|
||||
register "usb2_ports[9]" = "{
|
||||
.enable = 1,
|
||||
.ocpin = OC_SKIP,
|
||||
.tx_bias = USB2_BIAS_0MV,
|
||||
.tx_emp_enable = USB2_PRE_EMP_ON,
|
||||
.pre_emp_bias = USB2_BIAS_28P15MV,
|
||||
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
|
||||
}" # BT
|
||||
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1
|
||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
|
||||
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0
|
||||
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4
|
||||
|
||||
# Enable eMMC HS400
|
||||
register "ScsEmmcHs400Enabled" = "1"
|
||||
|
||||
# EMMC Tx CMD Delay
|
||||
# Refer to EDS-Vol2-14.3.7.
|
||||
# [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
|
||||
# [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
|
||||
register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
|
||||
|
||||
# EMMC TX DATA Delay 1
|
||||
# Refer to EDS-Vol2-14.3.8.
|
||||
# [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
|
||||
# [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
|
||||
register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911"
|
||||
|
||||
# EMMC TX DATA Delay 2
|
||||
# Refer to EDS-Vol2-14.3.9.
|
||||
# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
|
||||
# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
|
||||
# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
|
||||
# [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
|
||||
register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828"
|
||||
|
||||
# EMMC RX CMD/DATA Delay 1
|
||||
# Refer to EDS-Vol2-14.3.10.
|
||||
# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
|
||||
# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
|
||||
# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
|
||||
# [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
|
||||
register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b"
|
||||
|
||||
# EMMC RX CMD/DATA Delay 2
|
||||
# Refer to EDS-Vol2-14.3.12.
|
||||
# [17:16] stands for Rx Clock before Output Buffer,
|
||||
# 00: Rx clock after output buffer,
|
||||
# 01: Rx clock before output buffer,
|
||||
# 10: Automatic selection based on working mode.
|
||||
# 11: Reserved
|
||||
# [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
|
||||
# [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
|
||||
register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D"
|
||||
|
||||
# EMMC Rx Strobe Delay
|
||||
# Refer to EDS-Vol2-14.3.11.
|
||||
# [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
|
||||
# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
|
||||
register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515"
|
||||
|
||||
# Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them.
|
||||
register "PchHdaAudioLinkSsp1" = "0"
|
||||
register "PchHdaAudioLinkDmic0" = "0"
|
||||
|
||||
# Intel Common SoC Config
|
||||
#+-------------------+---------------------------+
|
||||
#| Field | Value |
|
||||
#+-------------------+---------------------------+
|
||||
#| GSPI0 | cr50 TPM. Early init is |
|
||||
#| | required to set up a BAR |
|
||||
#| | for TPM communication |
|
||||
#| | before memory is up |
|
||||
#| I2C0 | RFU |
|
||||
#| I2C2 | PS175 |
|
||||
#| I2C3 | MST |
|
||||
#| I2C4 | Audio |
|
||||
#+-------------------+---------------------------+
|
||||
register "common_soc_config" = "{
|
||||
.gspi[0] = {
|
||||
.speed_mhz = 1,
|
||||
.early_init = 1,
|
||||
},
|
||||
.i2c[0] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 0,
|
||||
.fall_time_ns = 0,
|
||||
},
|
||||
.i2c[2] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 0,
|
||||
.fall_time_ns = 0,
|
||||
},
|
||||
.i2c[3] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 0,
|
||||
.fall_time_ns = 0,
|
||||
},
|
||||
.i2c[4] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 60,
|
||||
.fall_time_ns = 60,
|
||||
},
|
||||
}"
|
||||
|
||||
# PCIe port 7 for LAN
|
||||
register "PcieRpEnable[6]" = "1"
|
||||
register "PcieRpLtrEnable[6]" = "1"
|
||||
# PCIe port 11 (x2) for NVMe hybrid storage devices
|
||||
register "PcieRpEnable[10]" = "1"
|
||||
register "PcieRpLtrEnable[10]" = "1"
|
||||
# Uses CLK SRC 0
|
||||
register "PcieClkSrcUsage[0]" = "6"
|
||||
register "PcieClkSrcClkReq[0]" = "0"
|
||||
|
||||
# GPIO for SD card detect
|
||||
register "sdcard_cd_gpio" = "vSD3_CD_B"
|
||||
|
||||
# SATA port 1 Gen3 Strength
|
||||
# Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB
|
||||
register "sata_port[1].TxGen3DeEmphEnable" = "1"
|
||||
register "sata_port[1].TxGen3DeEmph" = "0x20"
|
||||
|
||||
device domain 0 on
|
||||
device pci 14.0 on
|
||||
chip drivers/usb/acpi
|
||||
device usb 0.0 on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Front Left""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(0, 0)"
|
||||
device usb 2.0 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port Rear""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 3)"
|
||||
device usb 2.1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Front Right""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(0, 1)"
|
||||
device usb 2.2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Rear Right""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 2)"
|
||||
device usb 2.3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Rear Middle""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 1)"
|
||||
device usb 2.4 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Rear Left""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 0)"
|
||||
device usb 2.5 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
device usb 2.6 off end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Front Left""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "group" = "ACPI_PLD_GROUP(0, 0)"
|
||||
device usb 3.0 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Front Right""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "group" = "ACPI_PLD_GROUP(0, 1)"
|
||||
device usb 3.1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Rear Right""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 2)"
|
||||
device usb 3.2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Rear""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 3)"
|
||||
device usb 3.3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Rear Left""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 0)"
|
||||
device usb 3.4 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Rear Middle""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 1)"
|
||||
device usb 3.5 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end # USB xHCI
|
||||
device pci 15.0 off
|
||||
# RFU - Reserved for Future Use.
|
||||
end # I2C #0
|
||||
device pci 15.1 off end # I2C #1
|
||||
device pci 15.2 on end # I2C #2, PCON PS175.
|
||||
device pci 15.3 on end # I2C #3, Realtek RTD2142.
|
||||
device pci 19.0 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""10EC5682""
|
||||
register "name" = ""RT58""
|
||||
register "desc" = ""Realtek RT5682""
|
||||
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
|
||||
register "property_count" = "1"
|
||||
# Set the jd_src to RT5668_JD1 for jack detection
|
||||
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
|
||||
register "property_list[0].name" = ""realtek,jd-src""
|
||||
register "property_list[0].integer" = "1"
|
||||
device i2c 1a on end
|
||||
end
|
||||
end #I2C #4
|
||||
device pci 1a.0 on end # eMMC
|
||||
device pci 1c.6 on
|
||||
chip drivers/net
|
||||
register "customized_leds" = "0x05af"
|
||||
register "wake" = "GPE0_DW1_07" # GPP_C7
|
||||
register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)"
|
||||
register "stop_delay_ms" = "12" # NIC needs time to quiesce
|
||||
register "stop_off_delay_ms" = "1"
|
||||
register "has_power_resource" = "1"
|
||||
register "device_index" = "0"
|
||||
device pci 00.0 on end
|
||||
end
|
||||
end # RTL8111H Ethernet NIC
|
||||
device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
|
||||
device pci 1e.3 off end # GSPI #1
|
||||
end
|
||||
|
||||
# VR Settings Configuration for 4 Domains
|
||||
#+----------------+-------+-------+-------+-------+
|
||||
#| Domain/Setting | SA | IA | GTUS | GTS |
|
||||
#+----------------+-------+-------+-------+-------+
|
||||
#| Psi1Threshold | 20A | 20A | 20A | 20A |
|
||||
#| Psi2Threshold | 5A | 5A | 5A | 5A |
|
||||
#| Psi3Threshold | 1A | 1A | 1A | 1A |
|
||||
#| Psi3Enable | 1 | 1 | 1 | 1 |
|
||||
#| Psi4Enable | 1 | 1 | 1 | 1 |
|
||||
#| ImonSlope | 0 | 0 | 0 | 0 |
|
||||
#| ImonOffset | 0 | 0 | 0 | 0 |
|
||||
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
|
||||
#| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 |
|
||||
#| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 |
|
||||
#+----------------+-------+-------+-------+-------+
|
||||
#Note: IccMax settings are moved to SoC code
|
||||
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
|
||||
.vr_config_enable = 1,
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(5),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 1,
|
||||
.psi4enable = 1,
|
||||
.imon_slope = 0x0,
|
||||
.imon_offset = 0x0,
|
||||
.icc_max = 0,
|
||||
.voltage_limit = 1520,
|
||||
.ac_loadline = 1004,
|
||||
.dc_loadline = 1004,
|
||||
}"
|
||||
|
||||
register "domain_vr_config[VR_IA_CORE]" = "{
|
||||
.vr_config_enable = 1,
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(5),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 1,
|
||||
.psi4enable = 1,
|
||||
.imon_slope = 0x0,
|
||||
.imon_offset = 0x0,
|
||||
.icc_max = 0,
|
||||
.voltage_limit = 1520,
|
||||
.ac_loadline = 181,
|
||||
.dc_loadline = 181,
|
||||
}"
|
||||
|
||||
register "domain_vr_config[VR_GT_UNSLICED]" = "{
|
||||
.vr_config_enable = 1,
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(5),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 1,
|
||||
.psi4enable = 1,
|
||||
.imon_slope = 0x0,
|
||||
.imon_offset = 0x0,
|
||||
.icc_max = 0,
|
||||
.voltage_limit = 1520,
|
||||
.ac_loadline = 319,
|
||||
.dc_loadline = 319,
|
||||
}"
|
||||
|
||||
register "domain_vr_config[VR_GT_SLICED]" = "{
|
||||
.vr_config_enable = 1,
|
||||
.psi1threshold = VR_CFG_AMP(20),
|
||||
.psi2threshold = VR_CFG_AMP(5),
|
||||
.psi3threshold = VR_CFG_AMP(1),
|
||||
.psi3enable = 1,
|
||||
.psi4enable = 1,
|
||||
.imon_slope = 0x0,
|
||||
.imon_offset = 0x0,
|
||||
.icc_max = 0,
|
||||
.voltage_limit = 1520,
|
||||
.ac_loadline = 319,
|
||||
.dc_loadline = 319,
|
||||
}"
|
||||
|
||||
end
|
||||
Loading…
Reference in New Issue