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sb/intel/lynxpoint/acpi: Split USB into EHCI and xHCI 

Tested with BUILD_TIMELESS=1, Google Wolf does not change.

Change-Id: I0ce8f1e4aaa86d2f7607fec9214dc64d1f530c88
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46782
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-10-25 22:50:08 +01:00 committed by Michael Niewöhner
parent e15dc9eb1e
commit a82f06cb8f
3 changed files with 39 additions and 35 deletions
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34
src/southbridge/intel/lynxpoint/acpi/ehci.asl Normal file
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@ -0,0 +1,34 @@
/* SPDX-License-Identifier: GPL-2.0-only */
// EHCI Controller 0:1d.0
Device (EHCI)
{
Name (_ADR, 0x001d0000)
Name (_PRW, Package () { DEFAULT_PRW_VALUE, 3 })
// Leave USB ports on for to allow Wake from USB
Method (_S3D, 0) // Highest D State in S3 State
{
Return (2)
}
Method (_S4D, 0) // Highest D State in S4 State
{
Return (2)
}
Device (HUB7)
{
Name (_ADR, 0)
Device (PRT1) { Name (_ADR, 1) } // USB Port 0
Device (PRT2) { Name (_ADR, 2) } // USB Port 1
Device (PRT3) { Name (_ADR, 3) } // USB Port 2
Device (PRT4) { Name (_ADR, 4) } // USB Port 3
Device (PRT5) { Name (_ADR, 5) } // USB Port 4
Device (PRT6) { Name (_ADR, 6) } // USB Port 5
}
}

7
src/southbridge/intel/lynxpoint/acpi/pch.asl
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@ -67,8 +67,11 @@ Scope (\)
// PCI Express Ports 0:1c.x // PCI Express Ports 0:1c.x
#include <southbridge/intel/common/acpi/pcie.asl> #include <southbridge/intel/common/acpi/pcie.asl>
// USB 0:1d.0 and 0:1a.0 // USB EHCI 0:1d.0 and 0:1a.0
#include "usb.asl" #include "ehci.asl"
// USB XHCI 0:14.0
#include "xhci.asl"
// LPC Bridge 0:1f.0 // LPC Bridge 0:1f.0
#include "lpc.asl" #include "lpc.asl"

33
src/southbridge/intel/lynxpoint/acpi/usb.asl → src/southbridge/intel/lynxpoint/acpi/xhci.asl
View File

@ -1,38 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
// EHCI Controller 0:1d.0
Device (EHCI)
{
Name (_ADR, 0x001d0000)
Name (_PRW, Package () { DEFAULT_PRW_VALUE, 3 })
// Leave USB ports on for to allow Wake from USB
Method (_S3D, 0) // Highest D State in S3 State
{
Return (2)
}
Method (_S4D, 0) // Highest D State in S4 State
{
Return (2)
}
Device (HUB7)
{
Name (_ADR, 0)
Device (PRT1) { Name (_ADR, 1) } // USB Port 0
Device (PRT2) { Name (_ADR, 2) } // USB Port 1
Device (PRT3) { Name (_ADR, 3) } // USB Port 2
Device (PRT4) { Name (_ADR, 4) } // USB Port 3
Device (PRT5) { Name (_ADR, 5) } // USB Port 4
Device (PRT6) { Name (_ADR, 6) } // USB Port 5
}
}
// XHCI Controller 0:14.0 // XHCI Controller 0:14.0
Device (XHCI) Device (XHCI)